Tutorial: Optimizing Calibre DRC Rules for Maximum Performance
Presenter: Lei Ling
Org: Mentor Graphics

The Calibre hierarchical engine provides the best performance and capacity of any verification tool in the industry. With careful rule file writing, however, it may be possible to gain even better performance for DRC and LVS. This paper will present key concepts useful in the creation and maintenance of top performing rule files.

Basic concepts and skills for Calibre DRC Rule Optimization:

Workshop 1: Introduction to VHDL-AMS and Verilog-AMS
Author: Gary Pratt, Mentor Graphics
Time: 90 minutes

Abstract: Analog/Mixed Signal is coming soon to an IC near you. In fact, industry luminaries predict that most ICs will contain significant mixed-signal content by the year 2005. Mixed-Signal languages will play an essential role in the ability to design and verify these complex designs. This tutorial will provide a brief hands-on introduction to the VHDL-AMS and Verilog-A/MS analog extensions of the two dominant Hardware Description Languages.

Bio: Gary Pratt is the technical marketing manager for the analog/mixed-signal product group of Mentor Graphics, headquartered in Wilsonville, Ore. He is a graduate of the University of Wisconsin (Madison,WI), a member of IEEE, and a licensed professional engineer who has been practicing for 18 years. His career experience includes the design and design management of cardiac-image-processing hardware, multithreaded-image-processing software, and high-voltage/high-current PWM-amplifier systems. He has been an enthusiastic user of EDA tools for analog and digital system-, board-, and IC-level design and verification since 1982.

Workshop 2: LVS / PEX / Simulation Workshop
Author: Rajesh Prabhakar, Stuart Schwartz
Org: Mentor Graphics Corporation
Products: Calibre-LVS, Calibre-RVE, Calibre DesignRev , xCalibre, Eldo, MachTA

Abstract:
During this technical workshop, you will experience taking a design from LVS through parasitic extraction and into simulation. In the LVS phase, you will see the various approaches taken in recognition of devices in the design. For the extraction phase, you will see the benefits of using transistor level extraction vs. gate level. Simulation will include taking the design through the MachTA and Eldo simulators using the transistor and gate level extractions.

Bio:
Rajesh Prabhakar is a Technical Marketing Engineer for Mentor Graphics based in Wilsonville, Oregon. Stuart Schwartz is a Technical Marketing Engineer for Mentor Graphics based in Wilsonville, Oregon.

Workshop 3: LVS Debug Workshop
Author: Brian Marshall
Org: Mentor Graphics Corporation
Products: Calibre-LVS, Calibre-RVE, Calibre DesignRev

Abstract:
During this technical workshop, you will gain first-hand experience debugging common industry LVS issues. You will Learn how the use of hierarchical LVS and the Results Viewing Environment (RVE) can assist you and greatly reduce the time required for the debug process. The workshop will also include Mentor Graphics new gds viewing and editing tool, "Calibre DesignRev." This tool can be used to quickly view and edit gds data much faster and easier than other methods used in the industry.

• Learn the concepts of hierarchical LVS
• Use RVE to debug and fix power/ground shorts
• Use RVE to debug and fix LVS mismatches
• Use Calibre DesignRev to view and edit gds data

Bio:
Brian Marshall is a Technical Marketing Engineer for Mentor Graphics based in Wilsonville, Oregon.

Workshop 4: FPGA Advantage® - The Complete FPGA design flow solution
Author: Homayoon Larki
Org: Mentor Graphics Corporation

Abstract:
During this technical workshop, you will see a design taken from creation to synthesis in one smooth flow. Focusing on Block Diagram Editors, Interface-Based Design™ (IBD™), Tabular I/O, ModuleWare, OLE Documentation, HTML Documentation, and design debugging techniques. The FPGA Advantage flow delivers an integrated and easy to use solution for:

• Design Creation, documentation, & management
• Simulation and Debugging
• Advanced Synthesis

Bio:
Homayoon Larki is a graduate of Oregon Institute of Technology, where he received a Bachelor of Science degree in Electrical Engineering in 1988. He has been with Mentor Graphics since April 1990. His background is support, training and technical marketing in Design Entry, Simulation and Synthesis products. Homayoon currently works in the HDL Division as a Technical Marketing Engineer for HDL Designer Series and FPGA Advantage in Wilsonville OR.