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IC Design Technical Forum 2002
Mentor Graphics Users Group

IC Design Technology Forum Home Page Agenda Abstracts Keynote Workshops Travel Presenter Info

Agenda

Monday, April 15, 2002

7:30AM-5:00 PM Conference Registration Open
8:30-10:00 General Session
  Welcome - Uday Kapoor, Conference Committee Co-Chair, Sun Microsystems
  Invited Speaker - Joe Sawicki, General Manager, Physical Verification Division, Mentor Graphics
  KEYNOTE ADDRESS
Gadi Singer, Vice-President, Intel Corporation
10:00 - 10:30 Break
  ASIC/System/FPGA Track IC Design and Physical Verification Tutorials/Workshops
10:30 - 12:00 Robust DFT Methodology for Testing Tri-state Buses in SoC (Motorola)

Challenges of At-speed Scan in SoC (Motorola)

Transition Fault Test Generation in a Mega-ASIC (Sun)
Deploying CalibreMT in the Sun Microsystems Compute Farm (Sun Microsystems)

Using Calibre for Verification of the First 10 Gbps Network Processor ASSP
Introduction to VHDL-AMS and Verilog-A/MS (Mentor) Hands-on Workshop
12:00 - 1:30 Lunch and SIG Meetings
1:30 - 3:30 DFT Experience in NSC's Geode (tm) IA-on-a-chip (Natl. Semiconductor)

Reducing Simulation Mismatch Problems in DFT Implementations (Mentor)

Challenges with Today's System Level Design Approaches (Siemens)

Optimal System Level IP Realization in Autonomous Configurable Logic Design Flow (Leopard Logic)
Calibre DESIGNrev, Calibre Interactive, and Calibre RVE (Mentor)

Optimizing Calibre DRC Rules for Maximum Performance (Mentor)
FPGA Advantage - The Complete FPGA Design Flow Solution (Mentor) Hands-on Workshop
3:30 - 7:00 Partner Pavilion Vendor Fair


Tuesday, April 16, 2002

Time ASIC/System/FPGA IC Design and Physical Verification Tutorials/Workshops
8:30 - 10:30 BOF Meeting with Q&A - ASIC/FPGA Using Design Architect for Capturing Parasitic Parameters in Design Devices (Mitsubishi) Physical Verification in Addition to DRC/LVS (ST Microelectronics)
  Problem Solving in SDL (SliceX) LVS/PEX/Simulation Workshop (Mentor) Hands-on Workshop
Multiple Designer RF-IC Design Using Schematic Driven Layout and Process Design Kits (Advanced Bionics)
SDL: Using Filter Functions (Mentor)
10:30-11:00 Break
11:00 - 12:30 Designing High Speed PLDs using Embedded Processors (Mentor) A Mixed Signal Top-Down and Bottom-Up Approach for non-Volatile Memory Based Designs using ADMS (ST Microelectronics) BOF Meeting with Q&A - Physical Verfication
  When Fast-Spice isn't Fast Enough (Mentor)
  Debug Capability dramatically Effects the ROI on Formal Verification Tools (Mentor)
12:30 - 1:30 Break
1:30 - 3:30 BOF Meeting with Q&A - IC Design
IC SIG Meeting
Modularity in LVS Design (Chartered) Using Calibre in the Avant! Apollo Environment (LSI Logic)
Impact of RET on Physical Layouts (Mentor)

Configuation of IC Extraction Deck for CMOS process (Duke University)
LVS Debug Workshop (Mentor)
A Method of Viewing Large Parasitic Extracted RC Nets Using IC Station (Mentor)
3:00 - 5:00 Closing Reception with Awards

 

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