IC Design Technical Forum 2002
Mentor Graphics Users Group

Title: Reducing Simulation Mismatches Problem in Design-For-Test (DFT) Implementation
Author: Bambang Suparjo (presenter), Kevin King and Wu Yang
Products: Fastscan

Abstract:
Design For Test (DFT) is an approach to make a circuit/design testable after the completion of manufacturing process. There are two main areas in DFT; test pattern generation and test circuitry insertion. Test pattern can be generated using Fastscan and test circuitry can be inserted using DFTAdvisor. In general, the entire circuit/design is partitioned into smaller sub-circuits with memory elements as the sub-circuits’ boundaries, to enable the sub-circuits to be tested based on purely combinational logic. The memory elements are modified to become scan cells to provide data path to apply test data to the sub-circuit under test and to deliver out the test results for observation.

Since the test procedure is dependent on the type of scan cells e.g. mux-DFF or LLSD, it is essential to understand their operations not only in event-based operation but also in timing-based operation before implementing DFT in the design. This is to ensure the test procedure to be established is able to deliver correct data into and from the circuit under test while obtaining high test coverage. Without clear understanding on the operations, it will affect the overall chip development schedule where long time is needed in validating the test data before the design is sent for fabrication if the test data that being simulated on timing-based (using Verilog-XL or Modelsim) do not match those data generated from event-based simulation (using Fastscan). As an addition, the test circuitry might need to be modified and this might reduce the test coverage.

This paper discusses the simulation mismatches problems faced by designers and describes several methods to solve the problems. In general, most of the problems are related to DFT methodology such as incompatible test procedure with the chosen scan cell types, improper clock distributions for scan cells and incorrect simulation library models. Again, insufficient understanding in DFT methodology will require long diagnosis time especially for large design. For this reason, an approach to provide understanding on DFT methodology (related to simulation mismatches issue) for IC Designers before implementing DFT in the design is proposed.

Bio:
Bambang Suparjo is a Corporate Applications Engineer at Mentor Graphics Corp. (since July 2001) to support Mentor Graphics DFT products. Previously he has been a lecturer at Universiti Putra Malaysia for 15 years. He obtained his Ph.D degree from University of Southampton, United Kingdom in 1994. His research of interest is Digital and Mixed-Signal Design-For-Test.

Title: DFT Experience in NSC's GeodeTM IA-on-a-Chip
Author: Benny Rosen
Org: National Semiconductor (Tel Aviv design center)
Products: DFTAdvisor, DFTInsight, FastScan

Abstract:
We shall present the DFT work that was done in NSTA (NSC design center in Tel Aviv) on a large legacy IP: the SouthBridge module of National's "IA-on-a-Chip" chip family. This project was carried out through extensive use of Mentor's DFTAdvisor & fastScan tools, and with the extensive support of Mentor Israel.

We shall describe the problems that arose during the various phases of the DFT implementation and how they were resolved:

• DRC Problems
• Mixed design style
• Tristate buses
• DFT Bottlenecks
• Timing problems
• Verification issues

We shall present the tradeoffs for the generation of Production ATPG Patterns (Usage of 'minimum pins' vs 'all pins' of a chip, Vector count, Memory usage, Test time) and present the ATPG Testing results.

Bio:
Benny Rosen has been with National Semiconductor's design center in Tel Aviv since 1999. His responsibilities include Design for Test and Productization Support for National's Information Appliance chip family. Previously Benny worked for Motorola Semiconductor Israel where he was responsible for the Design & Test of 68xxx and PowerPC microcontrollers for the Automotive industry. Benny holds a BSc in Electrical Engineering from the University of Tel Aviv.

Title: SDL: Using Filter Functions
Author: William M. Drezen
Org: Mentor Graphics Corporation
Products: IC Station, Schematic Driven Layout, ICdevice

Abstract:
Understanding the application of filter functions with Schematic Driven Layout can provide the user a great deal of flexibility and solve many setup issues with the tool. The most problematic aspect of using filter functions is understanding how they are applied in practical user scenarios.

This paper will present a practical way to use filter function with real-world examples to illustrate some uses of the feature. The essential filter function modules will also be explained. The goal of this paper will be to equip the user with the essentials to begin using filter functions to solve tool setup issues and allow for customization.

Bio:
Bill Drezen is a Corporate Application Engineer with the IC support engineering team based in Wilsonville, OR and has been with Mentor Graphics since 1999. Bill has broad field experience using Mentor Graphics tools for IC mask design of data acquisition and DSP products and is an expert in SDL and IC ample customization. He previously worked in the semiconductor industry for 15 years as IC mask designer and as a CAD support engineer.

Title: A Mixed-Signal Top-Down and Bottom-Up Approach for Non Volatile Memory Based Designs using ADMS (VHDL-AMS)
Author: Pierluigi Daglio Carlo Roma (presenter)
Org: STMicroelectronics
Products: ADMS, Modelsim, Eldo-Mach, Mach-TA/PA, Calibre

Abstract:
The paper suggests a methodology for mixed-signal circuits development and analysis, promoting the usage of tools whose functionalities have been proven on Non Volatile Memories (NVM) technologies. The proposed top-down and bottom-up approach is based on the ADMS mixed-signal design environment from Mentor Graphics (MGC). Five major mixed-signal simulation steps have been taken into account: functional verification, behavioral VHDL-AMS simulation, digital VHDL/Verilog + analog VHDL-AMS + critical analog at schematic level, digital VHDL/Verilog + all analog blocks at schematic level, top level post-layout simulation with parasitic components.

All the main different levels of abstraction in mixed-signal simulation, where analog and digital domains can be processed together as a whole, have been investigated: functional, behavioral, mixed-signal and post-layout.

Functional level allows designers to verify circuit behavior using mathematical equations together with predefined libraries containing specific blocks with adjustable parameters. Functionalities are only verified from a pure mathematical point of view. Behavioral level allows to verify circuit behavior using a standard IEEE analog/digital behavioral language (VHDL-AMS) that lets designers describe both analog and digital blocks of their applications and simulate them in the Mentor Graphics ADMS environment. Analog blocks should be implemented using VHDL-AMS language while pure digital blocks are usually described with either VHDL or Verilog languages. Mixed-signal simulation level allows users to fit pure digital VHDL/Verilog, analog VHDL-AMS and schematic blocks according to the simulation needs. Schematic level blocks can be processed with Eldo and/or Mach-TA/PA engines according to the designer specific needs of speed and accuracy.

Post-layout simulation allows to evaluate behavior of the whole circuit with the parasitic components extracted with the Calibre flow. The overall parasitic netlist is flat and contains both analog and digital parts together at transistor level. Simulation is performed with Eldo-Mach and/or Mach-TA/PA engines.

Bio:
Pierluigi Daglio graduated in Electronics Engineering at Genoa University (Italy) in 1988 with a thesis on Neural Networks. He joined STMicroelectronics as an Applications Engineer in the Analog/Mixed-Signal Simulation field. After becoming a Senior Applications Engineer, in 1998 he took the responsibility of the NVM Analog/Mixed-Signal Design Flows Team. Since 2001, he has been appointed as NVM Mixed-Signal Design Flow Program Manager with the mission of understanding and investigating the needs of divisions as far as mixed-signal design flow is concerned.

Carlo Roma graduated in Electronics Engineering at Pavia University (Italy) in 1999 with a thesis on Bandgap Voltage Reference. He joined STMicroelectronics as an Application Engineer in the Analog/Mixed-Signal Simulation field and today he is working in the NVM Analog/Mixed-Signal Design Flows Team. He is expert in mixed-signal simulation methodologies.

Title: Optimal System Level IP Realization in an Autonomous Configurable Logic Design Flow
Author: Chris Philips
Org: Leopard Logic

Abstract:
This paper discloses the process from a design articulation in an RTL (Register Transfer Level) HDL (High-Level Description Language) to an optimal realization in a configurable logic solution. This has particular utility and application in fast moving, rapidly changing market areas such as in communications. Currently IP functions in this domain such as FEC (Forward Error Correction), packet processing, and protocol interfaces are implemented in fixed ASIC or discrete programmable logic solutions. Currently, this has served to be an impediment to the forthcoming $60B in revenue markets in key areas forecasted in 2005.

The Leopard Logic technology in conjunction with the Mentor Graphics design automation technology allows the conversion of "Star IP" quality Intellectual Property to be converted into a form which has several important characteristics vital to the future of ASIC SoC (System-on-a-Chip) design. The characteristics are comprised of meeting high performance level data throughputs, economical design, and robust reliable realization in a future proofed technology. This has been demonstrated by a process where RTL HDL Intellectual Property description is processed through a design flow comprised of the Mentor Graphics Leonardo Spectrum and ModelSim EDA tools in conjunction with Leopard Logic HDL libraries and conversion scripts. This results in an IP transformation that has provided proof of order of magnitude gains in cost, power, performance, and area for a customer based configurable logic solution.

Given the fact that 50-80% of today’s ASIC SoC devices fail on first silicon, a system technology such as that illustrated in the paper are required in order to address the challenges for current and next generation system silicon devices. This capability when used by the customer based provides an effective solution in order to enable the continued encroachment of electronics into everyday society in a myriad of application opportunities.

Bio:
Mr. Phillips has 20 years experience in microcontroller, microprocessors, FPGAs, ASICs, and CAD EDA tools at National Semiconductor, Summit Design, Integrated CMOS Systems, and Crosspoint Solutions. At Chameleon Systems, Inc. he was employee # 1 and President. He performed the product launch and introduction for the CS2112 product family as a featured Speaker in the Network Processor Segment of the Embedded Processor Forum 2000. The device received Product of the Year award from Electronic Products Magazine and nomination for MicroDesign Resources Architecture of the Year Award.

Prior to that, he was Director of High Level Synthesis at Summit Design handling products such as V-CPU, TriQuest, and DaSys. DaSys was a pioneer in the Behavioral Synthesis effort based on advanced research under Professor Don Thomas at Carnegie Mellon University.

Mr. Phillips served as Director of Advanced Architecture at Crosspoint on the innovative CrossFire FPGA family where he launched both a Top Down, Feed Forward Constraint based EDA tool set and a fully automated physical hardware array module constructor for anti-fuse based programmable product.

As the lead on the National Semiconductor/IIT and Microsoft at Work partner effort in the Integrated Processor Group, he designed the control and decode logic from the programmer’s reference manual to realize a fully compatible 486 processor engine from clean room design to functional silicon in 15 months.

In his career, he has a successful track record of 20 fully functional at first silicon device tape-outs. He has successful track record in business area’s of management, business development, sales, and marketing while mastering multi-disciplinary area’s in engineering of systems applications, micro-architecture, logic design, silicon level circuit design, algorithm invention, high level / assembly language programming, and code scripts. He has 17 patents granted to date. BSEE, Cornell University 1981.

Title: Robust DFT Methodology for testing Tri-State Buses in SoC
Author: James Thomas. Mike Mateya and Rekha Banglalore
Org: Motorola, Mentor Graphics (affiliation)
Products: Fastscan

Abstract:
The drive to achieve maximum functionality with minimum area poses many challenges for efficient DFT methodology. SoC’s are being designed and integrated with multiple IP’s to fit more system logic into the chip. As a result of embedding more logic into the chip, the bus transactions forms a critical aspect of system design. We see interfaces developed to control the internal tristate buses between cores and peripherals. There are a lot of well known techniques that can be used in the functional mode (normal working of the chip). However while testing the tristate buses during test modes requires careful analysis of the tristate buses to achieve maximum test coverage and test the buses without causing contention while the ATPG vectors are being tested on the tester.

This paper will focus on the different challenges of testing tristate buses like: (1) No bus master during scan modes of operation and its impact on testing and coverage (2) One module becomes the bus master during scan modes and its impact on the quality of testing and test coverage. (3) Finally the case of allowing multiple modules to drive the tristate buses during scan modes of operation. Approach 3 is the best approach that can be used in SoC’s to achieve maximum test coverage and efficiently test the tristate buses. However our case studies shows that this DFT technique will require some upfront methodology to analyze the behavior of tristate buses in functional mode and its impact on scan modes of operation. The results of our analysis indicates that diving into Fastscan’s tristate algorithm will greatly enhance the testing of these buses. Fastscan will analyze each module that can be active during scan modes and in addition multiple paths from the combinational logic will be analyzed to test the buses. The depth of combinational logic from the "D" cone of logic from the scan flops in the path of tristate logic will also affect how these buses will be analyzed by Fastscan during DRC and ATPG modes.

Mathematically the testability for the logic will be derived from Fastscan’s inherent algorithms internally. A comparison between the numbers for testability from the D cone of logic and the difficulty of testing will be measured. The result of our analysis will be a efficient DFT technique for SoC designs that will greatly reduce the ease of ATPG test vector generation from Fastscan. The result of improved DFT technique will be the significant decrease in the number of patterns that will be rejected during ATPG. The paper will also try to focus on the inability of Fastscan to detect problems in contention that can occur as a result of glitch in the path of combinational logic. Fastscan being a zero delay simulator cannot detect the glith which can appear in the path of tristate logic. These timing violations are generally seen during resimulation of scan vectors.

Title: Calibre DESIGNrev, Calibre Interactive, and Calibre RVE
Author: James Paris
Org: Mentor Graphics
Products: Calibre DESIGNrev, Calibre Interactive, and Calibre RVE

Abstract:
This two-part demo introduces Calibre DESIGNrev capabilities as a large capacity, lightweight revision tool, and covers Calibre Interactive and Calibre RVE use, and customization options.

The first half of this session focuses on Calibre DESIGNrev's fast GDSII viewing abilities by opening very large designs very quickly. Designed as a "lightweight" editor, and "heavyweight" viewing tool, DESIGNrev is capable of opening GDSII files of many gigabytes in just minutes. This live demo will introduce attendees to the operation of the tool, editing capabilities, and other features. DESIGNrev's ability to create custom macros makes this tool very versatile and useful within any design flow.

The second half of this session will demonstrate Calibre Interactive integration for interactive invocation of Calibre DRC/LVS and Calibre RVE's capabilities for fast efficient results debugging. Calibre Interactive and Calibre RVE enable single platform verification across many design environments, including Calibre DESIGNrev, Mentor Graphics ICStation, and Cadence's Virtuoso. Attendees will be introduced to customization options within Calibre Interactive, practical use of runsets, and get to see how Area DRC can save time when editing small portions of a large design. Calibre RVE users will also see new features within Calibre RVE that make this tool even more powerful.

Bio:
James Paris holds a Bachelors degree in CAD Engineering Technology, and has extensive background in layout design, physical verification from positions held as a senior layout engineer. He has also filled roles as a CAD engineer where he focused on design kit creation and methodology development. James is currently a Technical Marketing Engineer for the Calibre product at Mentor Graphics Corporation in Wilsonville, Oregon.

Title: Challenges with today's System Level Design approaches in real word systems
Author: Johann Notbauer
Org: Siemens AG Austria
Products: Seamless, HDL Designer, Modelsim, C-Bridge, Xray

Abstract:
Today's design processes are very often based on requirement and specification documents written in a natural language which are handed over to the hardware and software design teams, who then begin doing the implementation from scratch. There is usually no automated link between specification and implementation, what introduces problems and misunderstanding often detected very late in the design cycle. Today's system level design (SLD) approaches aim at closing the gap between the system's specification and implementation. So a system level methodology should supply an automated, tool-supported flow from the system's requirements down to transistors (for chips), netlists (for boards) or sw binaries.

Regarding SLD today's real word systems can be subdivided into dataflow and controller based architectures. SLD flows are working fine for dataflow and algorithm based designs. There is a seamless path from the high level definition down to DSP code or silicon.

Controller based architectures are also pretty well definable at the system level on a pure functional level. After adding timing information to the system level model, performance analysis is made possible. The next step is to decide which parts to implement in hardware and which in software. The timed system model has to be mapped to one or some different system architectures. After that the hard- and software design are done in different ways - each according to their well known flows. The hardware engineering team are adding some additional information, e.g. cycle accuracy. The software team has to introduce an operating system, which runs the application and accesses the hardware by hardware driver functions.

Both refinements steps are so far not covered by system level design tools or some automatism or synthesis step. So it seems that today's SLD flows and tools are not closing the gap between the functional/behavioral abstraction level and the actual implementation (RTL, board netlists, SW code) when applied to controller based real world designs.

This paper describes a very detailed system level design flow (for chip, board and sw components). Based on this it discusses how this works for the two mentioned types of designs. It highlights the phases in an ideal SLD flow already covered by tools and it especially concentrates on the design steps not yet covered.

Bio:
Johann Notbauer is Technical Director at Siemens‘ CES Design Center in Vienna/Austria. He joined Siemens in 1996, where he started his work in the area of verification of large and complex systems. The main part of his job was the successful integration of hw/sw coverification into the traditional design and verification flow. Since May 2001 he is the head of the CES chip design center responsible for ASIC, FPGA and IC layout design services. He is also author and co-author of publications in the field of electronic design automation. You can contact him at johann.notbauer@siemens.at

Title: Challenges of At speed scan in SoC
Author: Rekha Banglalore and Robert Cardwell
Presenter: Robert Cardwell
Org: Motorola
Products: Fastscan

Abstract:
This paper will examine the challenges of implementing at speed scan in SoC. At speed scan in this paper will refer to testing the scan vectors at the operating frequency of the part. Our case example will consist of stuck at patterns, transitional fault and path delay fault algorithm. The concept of at speed scan is at not new but there are several DFT related issues that are not well defined early on or implemented will lead to not achieving the goal of testing the part at speed. There is a difference between testing at speed scan for Microprocessor and SoC’s due to overheads in test logic, clock skews, pad delays and multiple cores in SoC’s that has to be defined and accounted for in the early design cycle to achieve the at speed scan in SoC.

This paper will focus on the following issues for SoC that can affect testing of at speed scan:

1. Test logic in the path of high speed cores
2. Clock skew issues
3. Analyzing the interaction of functional pins at speed scan during capture cycles

The paper will demonstrate the usage of tools like Fastscan which can be used very effectively in debugging at speed scan failures in simulation and silicon.

Title: Using Design Architect for Capturing Parasitic Parameters in Design Devices
Author: Russ Frazier
Org: Mitsubishi Electric and Electronics USA, Inc.
Products: Design Architect

Abstract:
Commonly used IC parasitic extraction tools will not extract parasitic RCs within a design device boundary, which leaves the parasitic circuit description up to a model for the device, if it exists. Available resistor and capacitor models may be inadequate for certain physical structures and so must be developed from primitives. This paper will describe a technique using Design Architect whereby parasitic RCs inside the boundary of a design device such as a p-diffusion resistor or a polysilicon capacitor can be captured for automated back annotation into an analog simulation SPICE file of the parent circuit. The method also provides a means of ensuring that the parasitic information matches the physical characteristics of the layout device and provides a record of how the layout device should be constructed. In addition, this method does not adversely affect IC Trace. After the user selects a schematic device a form function is run from a pull down menu and pops up with a set of text and number entry widgets specific to the selected device. The user fills out the form and the function does some data processing, then changes the schematic by altering properties. In our case, we alter a single property, either RESVAL or CAPVAL by setting the property value to a special text string. This text string contains the basic RESVAL and CAPVAL, as well as containing keywords and values that are used by a downstream netlister in the creation of the back-annotated SPICE file.

Bio:
Russ "Buck" Frazier held positions in the EDA industry at Avant!, Mentor Graphics and MEMScAP before joining Mitsubishi at the Design Engineering Center - East where he is now a senior CAD engineer. He has done work in software QA, rule file development, professional services, applications engineering, sales support, marketing, and system administration.

Title: Transition Fault Test Generation for a mega-ASIC
Author: Scott Davidson (presenter) and Paul Monschke
Org: Sun Microsystems, Inc.
Products: FastScan

Abstract:
It is well understood that covering stuck-at faults is no longer adequate to ensure high ASIC quality. Many defects, such as resistive bridges, cause delays in the circuit, and can only be detected by transition tests applied at speed.

FastScan provides an excellent capability for generating tests for transition faults. If you use the right tricks, you can not only get good transition fault coverage, but a test of reasonable size. We will begin with a short tutorial on transition faults, and on how transition fault tests are generated within FastScan. We will then describe transition fault test generation for a mega-ASIC of over five million gates. We have achieved very high coverage with no limit on vector count, and very reasonable coverage with a constrained number of vectors.

Bio:
Scott Davidson is Manager of the DFT Technology Group at Sun Microsystems. He has been working in the field of test for 20 years, first at Bell Labs, then at Intel, before coming to Sun. He is Area Topic Coordinator for Logic Test for the International Test Conference, Chair of the 2002 International Test Synthesis Workshop, Program Chair of the BAST Test Workshop, member of the Editorial Board of IEEE Design and Test, as well as editor of "The Last Byte" column there.

He has a B.S. from MIT, and M.S. from the University of Illinois at Urbana-Champaign, and a PhD from the University of Louisiana, all in Computer Science.

Title: A Method of Viewing Large Parasitic Extracted RC Nets Using ICStation
Author: Warren B. Wylie
Org: Mentor Graphics Corp.
Products: xCalibre and ICStation

Abstract:
With increasing clock rates resulting from shrinking transistor feature sizes in the modern integrated circuit the unintended influence of interconnect electrical parasitics is having a greater than ever influence in determining the success of a design. With clock rates now exceeding 1 GHz the risks of high interconnect resistance and stray coupling capacitance disrupting the intended functional of an IC is greater than ever. Therefore, the use of xCalibre, Mentor Graphics' parasitic extraction tool, is becoming more vital in the post IC layout verification stage of a design cycle. Unfortunately, xCalibre is capable of writing huge extracted net lists that are nearly impossible to correlate with the layout, even knowing the xy coordinates of each node of the RC net.

In this session, I will describe and demonstrate interactive userware that will selectively plot portions of the extracted net list directly upon an ICStation display of a layout pattern. Individual nets can be either selected as being within an area of the layout or picked off a menu list.

Bio:
Warren Wylie is a Corporate Application Engineer in the Customer Service Division of Mentor Graphics, where he is utilizing his 25 years experience in characterizing and analyzing the electrical behavior of layout patterns and components on ICs, hybrids, and PCBs in supporting xCalibre. Warren received his B. S. and M. S. in Physics from Kansas State University, specializing in the physics of thin metallic and III-VI compound films.

Title: Impact of RET on Physical Layouts
Author: Jody Draney

Abstract:
I will briefly discuss lithography development know as RET (Resolution Enhancement Technologies) including off-axis illumination in litho tools, Optical and Process Correction (OPC), and phase shifting masks (PSM). All of these techniques are adopted to allow ever smaller features to be reliably manufactured, and are being generally adopted in all manufacturing below 0.25 microns. Their adoption also places certain restrictions on layouts. I will explore these restrictions, and suggestions for practices that will facilitate the use of these technologies, generation of clean "target" layout for use as input layers for photomask preparation, and the use of verification tools that use process simulation.

Bio:
I'm currently a Corporate Application Engineer for Calibre RET. I have previously supported other EDA Products, specifically Calibre, Checkmate, ICGraph, Hot Plot, and CAECO. I enjoy delivering training and working with people. I have a BSCS from Weber State University and an MBA from the University of Phoenix. My hobbies include digital photography and music.

Title: Modularity in LVS Design
Author: Tree Nguyen
Org: Chartered Semiconductor Manufacturing
Products: Calibre-LVS

Abstract:
This paper will describe the innovative approach to rule file development that allows for the use of a single LVS rule deck to be used across numerous processes. Through Calibre’s easy to use SVRF and optimization during compile, this allows the ability to modularly recognize and extract devices. Statements for device recognition are independent and allow for easily adding new devices without effecting current recognitions.

Bio:
Tree Nguyen is a Technical Marketing Manager for Chartered Semiconductor Manufacturing in Milpitas, CA.

Seminar Session
Title: Designing High Speed PLDs using Embedded Processors
Presenter: Michael Bohm
Org: Mentor Graphics

Abstract:
Programmable Logic Devices (PLDs) have reached the level where true System-On-Chip (SOC) integration is possible. PLDs can now provide both the frequency and the density needed for most high tech development. The recent introduction of embedded micro-processors on the PLDs have created an architecture and a design methodology which could push the electronic industry to its next level of innovation. This seminar will provide design information and techniques for using the NIOS embedded processor from Altera.

Title: Using Calibre RVE in the Avant! Apollo Environment
Author: Keith Gallie
Org: LSI Logic
Products: Calibre-DRC, Calibre-LVS, Calibre-RVE

Abstract:
This paper illustrates the advantages of using Calibre Results Viewing Environment (RVE) in the Avanti Apollo place and route environment. In an ASIC design environment, the place and route tool is often the only editing tool used by design engineers at the top level. A complicating factor is that the final physical verification may not always be performed by software that has the same coordinate system as the place and route tool. This requires either coordinate translation or viewing errors in an environment in which the edits can not be saved. Having the ability to use RVE’s powerful viewing and debugging features in the place and route environment can greatly reduce the verification cycle time.

This paper also explains some of the integration limitations caused by the closed environment of Avant! and how these can be overcome with the recent enhancements to RVE.

Bio:
Keith Gallie is a Senior Design Engineer for LSI Logic based in Fort Collins, Colorado.

Title: When Fast-Spice Isn't Fast Enough
Author: Gary L. Pratt, P.E.
Org: Mentor Graphics
Products: ADMS, Mach-TA, Modelsim

Abstract:
In the beginning, there was darkness (multiple-fabrication spins). Then, Berkeley said, "let there be SPICE". And there was. And, it was good ... at least until simulation times grew to be measured in units of fortnights. Then, the industry said, "let there be Fast-SPICE". And, there was, and it was good too! ... at least until simulation times again grew to be measured in units of fortnights. Then, Mentor Graphics said, "let there be a real mixed-algorithm/mixed-language tool". And there was. And it was way good! And, it allowed the designer to abstract away complexity using analog or digital language models; use Mach-SPICE algorithms on more sensitive parts of the design; and use extremely accurate Eldo-SPICE algorithms for the extremely sensitive part of the design. And, the designers rejoiced and reveled in their newfound talents.

This paper will provide some examples of how the design cycle can be improved with the use of mixed-algorithm/mixed-language design and verifications tools.

Bio:
Gary Pratt is the technical marketing manager [and part-time biblical scholar] for the analog/mixed-signal product group of Mentor Graphics, headquartered in Wilsonville, Ore. He is a graduate of the University of Wisconsin (Madison,WI), a member of IEEE, and a licensed professional engineer who has been practicing for 18 years. His career experience includes the design and design management of cardiac-image-processing hardware, multithreaded-image-processing software, and high-voltage/high-current PWM-amplifier systems. He has been an enthusiastic user of EDA tools for analog and digital system-, board-, and IC-level design and verification since 1982. You can reach Gary Pratt at gary_pratt@mentor.com

Title: Using Calibre for Verification of the First 10 Gbps Network Processor ASSP
Author: Charlie Jenkins
Org: Fast-Chip, Inc.
Products: Calibre

Abstract:
Network processors are extremely difficult to verify. They are usually large and complex systems-on-chip containing components created with differing methodologies and a wide range of tools. It's an environment ripe for physical verification challenges.

Fast-Chip, Inc., a fabless semiconductor company that designs high-performance communications integrated chips, recently developed the breakthrough 10 Gigabit PolicyEdgeTM Services Processor. This 100-million-plus transistor IC can operate at an aggregate rate of 10 Gigabits per second across single or multiple ports; classifying, editing and maintaining statistics on 32 million packets per second [minimum packet size is 40 bytes each].

This paper describes Fast Chip's physical verification experience in completing tape-out, including their trials in identifying and employing a physical verification tool with the capacity to handle this large, high-speed chip. The Fast-Chip experience shows that even with an SoC as sophisticated as the PolicyEdgeTM, employing Calibre as the SoC verification tool is the key to accuracy, speed, performance and market goals.

Bio:
Charlie Jenkins is the Vice President of Marketing for Fast-Chip, Inc., a fabless semiconductor company founded in 1998 that provides component-level solutions for network equipment OEMs. \

Title: Deploying CalibreMT in the Sun Microsystems Compute Farm
Author: Fred James, Global Marketing Manager
Org: Sun Microsystems
Products: Calibre

Abstract:
Sun Microsystems innovative Compute Farm is a centralized network of powerful servers and workstations linked in a dynamically managed environment, sharing CPU cycles, memory, design tools, licenses and other critical resources. From the engineer's perspective, a well-constructed Compute Farm is a seemingly inexhaustible computational resource.

Calibre's multi-threading technology (CalibreMT) offers significant performance gain in a multiple CPU environment. Unlike other physical verification tools, which distribute multiple checks to each CPU in multi-threaded mode, Calibre's hierarchical processing engine passes separate pieces of data to each CPU. Calibre does this without increasing memory requirements or set-up constraints.

This presentation will describe the strengths of a Compute Farm, how to set-up and deploy Calibre in this environment, and the performance gains that can be realized when these two technologies work together.

Bio:
Fred James is the Global Account Manager-Mentor for Sun Microsystems

Title: How debug capability dramatically effects the Return on Investment of Formal Verification Tools
Author: Dr. Roger B. Hughes, Mentor Graphics

Abstract:
With ever reduced times to market and increasing design complexity caused by the system-on-chip (SoC) era of design technology more design teams are now relying on Formal Verification, especially equivalence checking, as an essential part of their design flow to ensure obtaining correct silicon on time. The return on investment (ROI) for equivalence checking tools varies considerably, with variations caused by differences in ease of insertion into the design flow, the ability of the tools to process large complex designs and by differing capabilities in error correction.

This paper will examine these differences and show how simple issues such as memory efficiency can have an impact on the verification approach. Using actual customer examples, it will discuss whether a hierarchical approach, with increased set-up time, is required; also considered are the possible side-effects of false negatives and how these affect debug time and ease-of-use. The author will examine how design debugging and error correction has impact on ROI, showing how the best tools enable design teams to quickly correct errors rather than just detect their presence. A rigorous derivation of the net benefit of formal verification tools versus the cost of insertion into the design flow will be presented together with recommendations on how to maximize the ROI.

Title: Multiple Designer RF-IC Design Using Schematic Driven Layout and Process Design Kits

Abstract:
In the era of short time-to-market, circuit and chip design must be parallel-tasked across a design team of varying expertise. Our design of a custom RF Transceiver chip for use in a cochlear implant product required the development of the system architecture, design cell interfaces and definitions, schematic generation, circuit simulation, circuit cell integration, layout, and simulation using extracted layout parasitics. The team consisted of four electrical and RF engineers, and a layout design specialist. Although the team had a great deal of electronic design and simulation experience, only one of the engineers and the layout specialist had previous experience in full-custom chip design. The design process flow stepped through architecture definition, cell design and simulation, cell layout, cell integration, layout extraction and simulation. Each designer performed each of the steps for his or her cells, as it progressed upward through integration.

The coordination of the design file structure was assisted by the involvement of the Mentor Application Engineers, our the MIS staff at Advanced Bionics. This allowed a tremendous simplification for the individuals not so experienced in the design flow. Specifically, a design kit was produced targeted for our specific MOSIS process. This made the schematic and layout environment a simplified menu/click sequence not requiring the usual intensity of directory and file management for most of the team. During layout, SDL (schematic driven layout) allowed rapid placement and routing of the design. Having preset layout rules enabled the less experience designers to focus on circuit interactions and best placement rather than details of width, clearance and file management. Although the process was still difficult, the design was successfully submitted. Three chips were submitted; two sub-cell chips, and a full chip. The sub-cells were submitted on the first planned run, whereas the full-chip was held back a month. The two sub-cell chips are now out of fab and in circuit test.

Bios:
Tissa Karunasiri-Analog design engineer experience in low power analog signal processing, twisted pair communication and power electronics. Current responsibilities includes design and fabrication of the audio front-end, power converters and neural response imaging system design on cochlear implants.

Diane Chu-- Electrical engineer with previous experience in digital electronics (DSP and gate array IC), presently working on becoming an RF IC design engineer.

Tae Hahn-- RF Engineer with experienced in Laser Sensors and its electronics, IFF systems. Presently developing RF systems for cochlear implants.

Glen Griffith-RF design engineer with experience in RF-CO2 lasers, laser electronics, aircraft identification electronics, and fiber-optic gyro electronics. Presently developing micro-power RF telemetry systems for cochlear and neural stimulation implants.

Wasantha Weerasinghe-- Presently working as a mask designer, with 2 years on Mentor IC Flow use. Prior experience includes working in a industrial research laboratory getting expose to calibration, measurement and electronics.

Title: Problem Solving in SDL
Author: Jon Thayer
Organization: Slicex, Inc., Nevada City Design Center

Abstract:
Schematic Driven Layout methodology can greatly enhance the productivity and accuracy of IC layout designers. Placement of devices is very fast, with absolute accuracy. With the use of fly-lines and cross-probing, intelligent placement of components is simplified. Top-down planning of port placement between sections can aid in critical signal flow planning. In addition, interactive and automated routing tools can be at the designer's disposal to aid in upper-level hookup of blocks.

In order to gain the advantages of using Schematic Driven Layout tools, interfaces between the schematic and layout databases need to be defined. Even after properly setting up your system for SDL, problems can arise that must be resolved. This paper discusses some approaches you can take to track down and resolve issues in an SDL environment.

Bio:
Jon Thayer has more than 24 years experience in CAD design for all types of electronic products, include Mixed-signal ICs, ultra-high density and high speed PCBs, MCMs, co-fired ceramic packaging, and flex circuits. Founder of 2 CAD design companies and an IPC certified interconnect designer, he is currently a Senior Layout Design Engineer with Slicex in Nevada City, California. His duties include project management of IC designs, analog and digital layout, advanced packaging design, and support of automated layout and verification tools.

Mentor Products: ICgraph SDL, ICdevice Digital and Analog, Design Architect

Title: Physical verification in addition to DRC/LVS
Author: Zia Ahmed
Org: ST Microelectronics

Abstract:
In this paper I would like to emphasize that only DRC/LVS are not sufficient for physical verification of any design / Chip . Let me begin by defining probe pad:-Probe pads are metal structures used for detecting the signal strength on chip optically i.e. by electron beam .They bring the signal in lower metal to higher metal thru a set of vias to highest metal of an appropriate opening . They play extremely important part in helping the debugging of the chip, as they could allow us to probe the signal strength internally without influence of external factors like cell delay/ probe pin cap...etc .

But there is no means till date if any of the vias in the probe pad is missing / deleted accidentally in the layout. But in ST microelectronics we have developed a technique for checking the same which IS NEITHER drc/lvs check but ebeam check. This check uses the calibre extraction flow with modification in the techfile and the layer map table . The gds2 translation is restricted to metals and extraction is limited to shorts determination and exludes devices etc .This process is extremely fast and helps the designer to check the probe pad entity as such . It also gives the location of those pads placed and hence helps in providing necessary testing information .

This is a summary of a real test problem
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A testchip fix project had come in which memory was failing and it was not possible to debug as E-beams probe had vias missing and was not checked at any level neither DRC/LVS .So a fix was to be resent and we had to make sure that this is not repeated .I had developed a script and a technique to detect the E-beams ,their connectivity and also the shielding from noise by ground net .Even till date there is no other way out to detect the same.

Bio:
ST , Singapore
Experience :- (~ 4 years)
Joined ST after completing MTech from Delhi Univ in 1998 as Associate Dsign Engineer. Worked with a team responsible for Developing Testchips for CRnD products like Memories (ROM,SRAM etc) and Std Cells for every technology .Had also worked with the memory development team to develop layout for SRAM memory .

Presently working as IC Design Engineer II in ST smartcard div Singapore. Responsible as Team leader for the BE activity from schematic to Tape out and also Testing . Brief of activities include
- stabilize the BE flow for the Smartcard Singapore
- To carry out BE activity from Floorplan to Tape Out and Mat 20 finally
- To innovate new ways of Carrying out BE activities .
- To improve yield and first time success on Silicon .

Area of Expertise:
BE floorplan, PnR, Power management ,Extraction , Timing Analysis, and Final verification and hence tape out of product.

Mentor product: Calibre

Title: Configuration of IC Extraction Deck for CMOS process
Authors: Himanshu Arora (presenter), Dr. James Morizio
Org: Duke University

Abstract
Mixed-Signal designs require correct estimation of device and interconnect parasitic to obtain a close correlation between chip test results and simulation data. This paper presents concepts for developing an extraction deck for interconnect and device parasitics for a N_Well CMOS process. The deck is calibrated with a Mosis 31-stage ring oscillator for extracting the device parasitics namely Area of Source and Drain (AS, AD); Perimeter of Source and Drain (PS, PD); Number of Squares of Source and Drain diffusion (NRS and NRD). The deck was also configured for extracting intrinsic; crossover and nearbody interconnect capacitances.

Bios:
Himanshu: Graduate Student at Duke University. Masters in Mixed Signal VLSI at Duke University. Did Undergraduate in India from REC Warangal in 1996. Was involved in Industrial R&D in Asea Brown Boveri and CMC India for around three years. Currently pursuing PhD at Duke University in RF IC design.

Dr. Morizio: Adjunct Professor at Duke University in Mixed Signal VLSI.