IC Design Forum Abstract

Title: Impact of Configurability on ASIC SOC Design Methodology
Author: Chris Phillips

Abstract:
System on a Chip designs now require configurable hardware capability. This requirement is especially evident in today's and tomorrow's communications oriented devices. The compelling force that is driving the requirement for configurability is the relentless squeeze between system complexity and time to market. A configurable hardware core with a fully integrated design tool methodology will be the key enabler for the tough SOC issues of risk mitigation, design reuse, and tool methodology.

Time to market has become a dominant determinant of market share and product profitability. Communication product life cycles have shrunk to 6-12 months which leads to development times of only 3-6 months. At the same time, economic factors are increasing the complexity of SOC design. As the ASIC device geometries continue to march forward in greater densities, the costs associated with each new process generation continue to scale at an even greater rate. Economies of scale will always favor the larger integration, higher density silicon device realizations.

The answer to the above contradictory objectives relies on the effective deployment of configurable capability in ASIC SOC devices. This in turn is directly related to ASIC SOC design methodology issues.

Communication oriented devices typically target evolving standards and protocols that are being designed by committee. This inherently leads to increased risk and longer development times. Embedding a configurable core onto an SOC allows the system designer to apportion blocks of logic with some future margin for the inevitable design changes. The best solution is to use hard coded blocks for well defined high complexity blocks such as microprocessors and memory, while using configurable hardware for blocks subject to change such as communication protocols.

In prior generations of system design, boards were constructed by teams of people who were specialists in their respective domains of knowledge. This included experts in board layout, ASIC design, FPGA design, DSP programming, microcontroller programming, real time OS development, and other diverse components. These formerly segmented development efforts now must be applied within the context of a single design methodology. Given that many of tomorrow's system designers were former DSP programmers, a key enabler will be ease-of-use. Unless there is an integrated tool framework, with reasonable transitions between design domains, ASIC SOC deployment will continue to suffer from slow adoption. Any hope for continuity in the design tool flow must be based on an underlying continuity in the hardware platform.

Any configurable module must allow specification with standard RTL in Verilog or VHDL formats. This is the only path to integration with the existing wealth of logic synthesis, logic simulation, and co-simulation tools. Today's ad hoc ASIC practice of including a plethora of configuration registers is not only proprietary, but unsupportable by any generic tool flow.

To facilitate the design of a large scale SOC by system designers, the use of verified and modifiable Intellectual Property (IP) blocks is desired. These must be specified at the highest abstraction level possible in order to allow easy incorporation into system level design and verification tasks, as well as to allow modification based on system level optimization. Virtual function calls, encapsulating the hardware function and memory mapped interface, are required to integrate into the designer's program and debug tools.

The verification of communications devices typically involves running millions of test vectors at speed. Configurable IP blocks which can be monitored, modified, and downloaded to the actual production silicon running within a test bench will offer significant verification and optimization advantages. This capability should be delivered to the system designer via a comprehensive library of software drivers.

The configurable logic needs to support physical ASIC integration as well, with transparent tool support. This includes offering variable sizes and aspect ratios for ASIC floorplanning; low level physical design representations such as GDSII data; place and route pick-up point layer, feed-through, and text definition; and physical timing annotation data. The Caliber and Xcaliber tools provide the capability to provide manufacturable layout and accurate DSM physical interaction information to create back annotated SDF timing data.

The last key to ASIC SOC methodology is an incorporation of system level integration and verification. The configurable logic should offer BSDL and BIST direct support for a global test generation tool such as FastScan and FlexTest. The other issue is that up to 80% of an SOC total design cycle is actually spent on the software development and it's attendant hardware module integration. Usage of a co-verification product such as Seamless becomes mandatory to allow concurrent software development and interplay from the microprocessor to new logic block development.

By leveraging the best of art design and methodology practices, the proper mix of hard wired optimized blocks with flexible configurable blocks results in the best solution to meet the goals of high density, high speed, low power, low risk, and fast time to revenue. As the Microprocessor core has had a fundamental impact on today's ASIC SOC designs, the Configurable core will play an increasingly important role in future SOC designs.

Bio:
Recent talks include being a featured speaker at Embedded Systems Conference 2000 on Communication Processors. Other papers include FPL2000 on Adaptive Processing for CDMA2000. Mr. Phillips has 20 years experience in microcontroller/microprocessors, FPGAs, ASICs, and CAD & EDA tools at National Semiconductor, Summit Design, Integrated CMOS Systems, and Crosspoint Solutions. Most recently he was the founder and CTO at Chameleon Systems, Inc. Prior to that, he was Director of High Level Synthesis at Summit Design, Director of Advanced Architecture at Crosspoint on the innovative CrossFire FPGA family, and key contributor at National Semiconductor in the Integrated Processor Group on an effort that saw a fully compatible 486 processor from clean room design to functional silicon in 16 months. He has 15 patents granted to date. BSEE, Cornell University 1981.