Due to popular demand, we have again expanded our selection of conference workshops at MARLUG 2007. Many attendees find these workshops to be one of the most valuable parts of the conference, and a great opportunity to gain hands-on knowledge of Mentor products.

All registered attendee's of MARLUG are invited to attend a hands-on workshop on Tuesday, Oct. 9th at Johns Hopkins University. Workshops are in-depth, hands-on training sessions for all levels of users, and are either half day or full day in length. Workshop materials are available for every attendee.

Please arrive at the workshop early to ensure access to a system. Doors will open at 7:30 AM. There may be up to 2 attendees per workstation.

Morning Workshops (8am-12pm)
Xtreme PCB Design
HyperLynx 7.7
Object Oriented Concepts for Functional Verification

Afternoon Workhshops (1pm-5pm)
Fablink XE
Advanced Constraints and Routing
Creating Object Oriented Test Benches for Real World Applications

Morning Workshops

Xtreme PCB Design
8am-12pm

In this workshop users will see how to start an Xtreme session. We will then have all of the participants connect to the server and route different sections of the board.

*Prerequisites: Basic knowledge of Expedition or Board Station RE Layout environment is required.

HyperLynx 7.7
8am-12pm

In this course, you will learn how to best utilize the new features found in HyperLynx 7.7. Some features include increases in usability such as unlimited probes, automatic waveform measurements, and batch simulation enhancements. Other features highlight new technology built into HyperLynx 7.7, such as Fast Eye diagrams, what-if via modeling and analysis, and the integration of our Analog/Digital Mixed-Signal (ADMS) simulator. Both types of features will be examined in instructor-led lecture and hands-on lab exercises.

*No prerequisites are required, however, a basic understanding of HyperLynx is beneficial.

Object Oriented Concepts for Functional Verification
8am-12pm

Hardware verification languages with object oriented constructs are now the dominant mechanism for the development of functional verification environments. Hardware engineers often find themselves unfamiliar with these historically software oriented concepts. This workshop is designed to familiarize engineers with object oriented concepts that they will use in developing advanced verification environments. Topics will include procedural vs. OO programming, classes, objects, inheritance, polymorphism, interface vs. implementation, constructors, data scope, and designing a class with reuse, extensibility and maintainability in mind. All examples and class exercises will be in System Verilog.

*No prerequisites are required, however, familiarity with functional verification processes with Verilog and/or VHDL and exposure or experience with hardware verification languages and/or OO programming is beneficial.

Afternoon Workshops

Creating and Manufacturing Outputs and Documentation with FabLink XE
1pm-5pm

When designers have completed a design with Expedition PCB, they can only create a limited amount of automated output information (i.e., Gerber, NC Drill). These users have had to rely on their fabricators, assemblers, testers and stencil manufacturers to help create the outputs and the finished product correctly the first time.

For those who have wished to generate all of the data, the Mentor Graphics System Design Division has created two tools that will empower our users to do so. This hands-on workshop will take a finished design and walk the participants through:

• Compiled validation of a design


• Creating finished panel, and


• Creating all related documentation


• The Batch DFF analysis module identifies any potential fabrication issue based on design rules that the user can import or create.

FabLink XE provides the users the automatic/interactive funcationality to place a single, unique design within the 6 families of panels. FabLink XE Pro provides this same functionality, plus functionality to place multiple unique designs within a single panel. The Drawing Editor will allow the user to create scalable documentation, including fully dimensioned detailed views. This user can choose between any of the three dimensioning methodologies (associative; geometric, also known as GD&T; and ordinate).

*Prerequisites: Basic knowledge of Expedition or Board Station RE Layout environment is required.

Advanced Constraints and Routing
1pm-5pm

This workshop covers advanced capabilities in CES to handle everything from parallel, multi-drop busses such as DDR memory interfaces, to super-fast serial interfaces based on differential signaling. Hands-on labs show how the routing environment handles these advanced constraints.

*No prerequisites are required, however, a basic understanding of CES is beneficial.

Creating Object Oriented Test Benches for Real World Applications
1pm-5pm

SystemVerilog is a Hardware Verification and Design Language that can be used to verify logic designs represented in Hardware Design Languages, such as Verilog and VHDL. The SystemVerilog language standard implements many software centric constructs, such as object oriented programming, abstract data types, and inheritance. By applying software techniques to the verification problem, engineers can be more efficient and productive in the logic verification process. Object Oriented software design aspects can also be leveraged to produce modular, re-usable test benches from standard base-class verification libraries. This workshop is intended to familiarize engineers with how to construct an object oriented test-bench using the Advanced Verification Methodology (AVM) from Mentor Graphics Corporation. AVM is Mentor’s Open-Source solution to providing a standard verification library that can be used to implement verification environments for logic design projects. The class will become familiar with AVM based verification environment architecture, integrating test-bench components, and varying stimulus to the design-under-test while collecting functional coverage using an example design under test.

*No prerequisites are required, however, familiarity with functional verification processes with Verilog and/or VHDL and exposure or experience with hardware verification languages and/or OO programming is beneficial.