Keynote
Expedition
PADs
General
High-Speed
IC-ASIC
FPGA
Schedule (pdf)

Technology Leadership through Innovation – Meeting the Challenges
Wednesday, October 10 • 9:00am – 10:00am
Henry Potts, General Manager: Systems Design Division, Mentor Graphics

The demands for increasingly competitive products is driving the electronics industry to advanced PCB fabrication technologies, the use of innovative design methods to cut cycle time and reduce product costs, and expansion of design team collaboration outside of the PB space. Mr. Potts will discuss industry trends into new manufacturing methods citing market data and case studies where cost and performance tradeoffs were made. He will talk to Mentor’s development processes for leading technology and cite specific examples of some new functionality and future development directions both within the PCB design space and extended into IC and mechanical design team collaboration.

Biography

Henry Potts joined Mentor Graphics in March of 1999 as Vice President and General Manager of the Systems Design Division. Potts brings more than 33 years of experience in the electronics industry to his role at Mentor Graphics, including experience in IC & Systems development, to serving as president and CEO of a venture capital funded startup. He served as a Senior Vice President for Hitachi Semiconductor where he oversaw all marketing and product development activities for microprocessor and embedded products for the US markets. He has also held senior management positions at Motorola, VLSI Technology, Schlumberger and Texas Instruments. Potts has a BS degree in Electrical Engineering from University of Southwestern Louisiana.

Go Green: Conserve Energy and Find it Fast on New SupportNet
Wednesday, October 10 • 3:00pm – 4:00pm
Christine Egli, Worldwide Customer Support Web Director, Mentor Graphics

With the launch of the new SupportNet, Mentor's most popular renewable resource now saves even more tine and energy for your design teams. The personalized site eliminates waste with faster problem solving, easier downloading, and service requests that are just a few clicks away. Learn how to troubleshoot critical issues with sustainable solutions from Mentor experts. Understand how SupportNet, our energy-efficient support site, is friendly to your design environment.

Automation for the Expedition Enterprise Flow
Wednesday, October 10 • 10:00am – 11:00am
Kendall Hiles, Global Applications Engineer Consultant, Mentor Graphics

Moving to SMT 0201's? Using HDI technology and want to sort nets on the Z axis or find and fix your dogbone issues? Want to add IPC-2221 current calculations to CES? Need to read test fixture data from another board or from another CAD system? From introducing new technology to supporting manufacturing, keep productivity up and costs down by automating your tools. Come see how to write automation and get a collection of userware that AE's and users have created to solve problems in DxDesigner, CES and Expedition.

Closed-Loop High Speed Design Process
Wednesday, October 10 • 11:00am – 12:00pm
Ned Dempsher, Signal Integrity Expert, L-3 Communications
Ted Lin, Applications Engineer, Mentor Graphics

The concept of closed-loop process is nothing new in automation and control systems. A closed-loop process is the key to stability, consistency, and high quality. However, implementing a closed-loop process in high speed digital design may still be foreign to some engineers.

In this presentation, we will introduce the concept of Closed-Loop High Speed Design Process. We will use Signal Integrity Simulation tools to build and validate the design rules, use CES (Constraint Editor System) to enter design rules and drive Expedition AutoRouter to test route the high speed PCB traces. Signal Integrity Simulation tools such as HyperLynx and ICX can be used to verify the PCB design and export selected traces for what-if design optimization. The optimization results then can be captured by CES and complete the closed-loop design process.

Package Type to Package Type Placement
Wednesday, October 10 • 1:00pm – 2:00pm
David Long, CAD Librarian, Scientific Atlanta, A Cisco Company

This presentation covers package type to package type placement using CES. It will also explore “added” package types to CES and Expedition and adding package type-to-package type spacing. The presentation concludes with an explanation of how it all works together.

Expedition Enterprise Update
Wednesday, October 10 • 2:00pm – 3:00pm
Glenn Dickow, Business Development Manager, Mentor Graphics

This presentation is an overview of the most recent enhancements to Expedition PCB and the projects that are currently in the pipeline for the release in 2007 and beyond. The session includes AVIs and detailed discussion about its functionality.

Reverse Engineering Gerber Files
Wednesday, October 10 • 10:00am – 11:00am
Ray Fugitt, Technical Marketing Manager, DownStream Technologies

Reverse engineering is the process of starting with Gerber files then adding part and netlist information, to create an intelligent database. We will start a Gerber file, create a netlist, build parts, add the part information to the Gerber files, and export a PADS ASCII file. We will then bring this into PADS Layout. Along the way, we will show tips and tricks for each part of the procedure, as well as have Users who have done this procedure available to answer questions. Reverse Engineering is important if you have an archive of old designs – stored as Gerber files or in another CAD database – that you wish to view, use, or convert to your new system. With the right tools, you can reverse engineer those files to be useful again.

Tips & Tricks with PADS & High-Speed
Wednesday, October 10 • 11:00am – 12:00pm
Ernie Frohring, Senior Applications Engineer, Trilogic

High end layout systems available today are often used for designs involving high speed constraints. But PADS users are sometimes called upon to work on high speed designs as well. We will discuss and demonstrate how to work with minimum, maximum and match length rules, differential pairs, electrical net rules, net scheduling and virtual pins using the PADS Flow design tools.

HyperLynx PELE (Pre-Emphasis and Equaliation Link Estimator)
Wednesday, October 10 • 1:00pm – 2:00pm
Bob Hedrick, Altera

With the proliferation of high speed serial protocols using today’s gigabit transceiver technology, it is important for the system designer to be able to efficiently take advantage of all the transceiver capabilities available by combing the latest transceiver technology with the latest EDA tool technology.

Protocols such as Gbe, XAUI, PCIe, Serial RapidIO and many custom backplanes now using the CEI 6G specification are already prevalent. Many of these applications are simply going faster using legacy interconnects. Examples of these protocols include XAUI (3.125G -> 3.75G), PCIe Generation 2 (2.5G -> 5G), and Serial RapidIO 3.125G -> 5G). Also, many applications are using cabling schemes to arrive at cost effective solutions.

The Altera Stratix® II GX 6-Gbps transceiver has thousands of possible voltage, pre-emphasis and equalization settings available. The PELE tool integrated into Hyperlynx with the Stratix® II GX kit allows the user to quickly get an approximation of what the signal eye opening would be for a selected channel. The tool generates the transceiver pre-emphasis and equalization settings so that detailed channel simulations can be performed.

This presentation will touch on pre-emphasis and equalization and how the various transceiver settings affect the serial waveform. It will review the PELE functionality within Hyperlynx.

PADS Product Update
Wednesday, October 10 • 2:00pm – 3:00pm
Jim Oakley, Technical Marketing Engineer, Mentor Graphics

PADS users will not want to miss this product update session, covering the new PADS 2007 RF design support, interactive high-speed routing, alphanumeric pin support, revised free design database translators and much more!

Macrovision’s FLEXNet – Hype or Hope?
Wednesday, October 10 • 10:00am – 11:00am
Rachel Stanley, License Administrator, Honeywell

We all have heard the sales pitch for FLEXNet Manager, but what is the truth? This session will compare and contract FLEXNet Manager with SAMSuite/SAMReport based on real world experience. In addition, this session will also cover what are the real benefits of investing in FLEXNet, as well as what we found that improved our lives, what surprised us and what made our lives more difficult.

Customizing your Search with the MGC Documentation System
Wednesday, October 10 • 11:00am – 12:00pm
Sarah Leritz-Higgins, Senior Technical Writer, Mentor Graphics

The centerpiece of the MGC Documentation system is InfoHub, a directory of locally installed documentation. The InfoHub provides links to the documentation, in both HTML and PDF. In addition to the directory, the InfoHub provides a flexible search interface. The InfoHub is customizable, enabling you to include links to design documents or sites that are specific to your organization. Also, from InfoHub, you can submit a product-specific search directly to SupportNet.

Introducing BluePrint for PCB Documentation
Wednesday, October 10 • 1:00pm – 2:00pm
Joe Clark, Co-Founder, DownStream Techologies

BluePrint-PCB Offers a Revolutionary Solution for Creating PCB Documentation. Current tools and methodologies for PCB Documentation are essentially workarounds that, rather than automate, create obstacles to producing detailed and accurate PCB documentation. DownStream will show how BluePrint removes these obstacles and creates your PCB documentation with ease. Import your design data, click through the menus, create customized notes and instructions, watch your electronic documents come to life. You will see how easy it is to create PCB documentation faster, with greater detail, while lowering your company's overall cost. Plus, discover how easy those ECOs can become.

• BluePrint requires one single load of the entire PCB CAD database to start the documentation process, and uses all the CAD intelligence to create the documentation.


• Print uses a drawing and sheet-based approach to create actual PCB documents (drill drawing, assembly drawing, parts list, etc) and stores them in an electronic release package.


• Print uses the CAD data to automatically create unlimited views, details, and charts of the PCB and can revise the documentation to reflect new PCB changes in seconds.


• changes are incorporated by “refreshing” the source CAD data. BluePrint “ripples” the new PCB data throughout the documentation package, updating every instance of a PCB View, detail, and chart.


• BluePrint is developed in the style of Microsoft Office to ensure quick adoption into your facility by making it familiar and easier to learn and use.

Board Station XE: The Next Generation Design Flow
Wednesday, October 10 • 2:00pm – 3:00pm
Steve Shively, Board Station XE Product Marketing Manager, Mentor Graphics

Board Station XE was launched with the BSXE2006 release last fall. Since then, customers are designing more complex boards than before, and they are doing this in less time. This Product Update presentation will provide insight into how this is being done with the new Board Station XE flow.

The High-Speed Serial link Designers Survival Guide
Wednesday, October 10 • 9:00am – 10:00am
Eric Bogatin, Signal Integrity Evangelist, Bogatin Enterprises
Presented by: Pat Carrier, Technical Marketing Engineer, Mentor Graphics

In this session, we will review the 4 interconnect problems in high-speed serial links and what can be done to minimize the hit from the interconnect. The four problems are: losses, reflections, intra-line skew and cross talk.

Using Hyperlynx 7.7 for Batch Mode for Inter-Component and Multi-Board Simulations
Wednesday, October 10 • 10:00am – 11:00am
Alex Golian, Northrop Grumman

Present day high performance, high speed, mixed signal applications, often require high speed, multi-bus register to register transfers between densely routed FPGA interfaces, and FPGA and DDR memory interfaces. In addition, these noisy interfaces must coexist with sensitive RF and analog signals on the same printed circuit boards to reduce size. For better isolation it is more practical to keep noisy digital circuitry and sensitive RF and analog circuitry on separate printed circuit boards. As a result, for proper risk mitigation, it has become necessary to not only simulate dense, high speed digital interfaces between components on the same printed circuit board, but also between different PCB’s via high performance inter- printed circuit board connectors.

Since it is impractical to simulate hundreds of signals one signal at time to uncover signal integrity issues such as crosstalk, overshoot, and excessive attenuation, batch mode simulation capability is essential. This report will present Hyperlynx 7.7 batch mode, and multi- printed circuit board simulation capability. It will show how these capabilities can be used to simulate, among other things, dense routing between not only components on the same printed circuit board, but in combination with its multi-PCB simulation capability, dense routing of component signals between multiple printed circuit boards. The report will also show that the set up for batch mode and multi printed circuit board simulation is simple, and the capability is powerful.

HyperLynx
Wednesday, October 10 • 1:00pm – 2:00pm
Bob Hendrick, Altera

High-Speed Product Update
Wednesday, October 10 • 2:00pm – 3:00pm
Pat Carrier, Technical Marketing Engineer, Mentor Graphics

In light of Mentor’s ongoing heavy investment in high-speed tools, the High-Speed update presentation provides an overview of the many recent improvements made to our high-speed tools, as well as where they are headed in the future. The presentation will outline recent enhancements to HyperLynx 7.7, including industry-leading technology such as Fast Eye diagrams and what-if via analysis, in addition to the recently released ICX Pro Verify, as well as enhancements in ICX and ICX Pro Explorer. A lively Q&A session will follow.

Enabling MPRUN in Eldo/ADMS -- Problems and Solutions
Wednesday, October 10 • 9:00am – 10:00am
Abhishek Bhaduri, CAD Engineer, Cypress Semiconductor

We, at Cypress, are trying to make the switch to MPRUN for launching jobs through our corners engine for more than two quarters now. We have identified some issues with MPRUN and have solved some of them and others are still in R&D stage. Both at Mentor (as ER/DR) or at Cypress. This presentation will cover the work that has been done in enabling MPRUN in Cypress and how it has affected us. The items I will cover are license savings, impact on runtime and disk usage, known defects and avoidance, implementation issues etc.

Fast ECO Closure using Calibre
Wednesday, October 10 • 10:00am – 11:00am
Rajesh Bansel, Freescale
Priyanka Bhan, Freescale

Engineering change orders (ECO) have now become unavoidable in chip design. Traditionally ECO implementation was carried out using either an APR (Auto Place and Route) tool or a layout editor. Both of these tools have shortcomings such as being time consuming, labor intensive, repetitive in nature and lack of feasibility. This paper proposes an innovative method of processing ECOs using Calibre, which is free from shortcomings of traditional approaches. The inputs for Calibre are obtained using the APR tool and existing GDSII. The operations incorporating the ECO are performed on the Golden GDSII using a derived Boolean expression. Discussed in the paper are details about how the inputs to Calibre are created, and how Calibre speeds up the ECO implementation process and bridges the gap between the Golden GDSII with the ECO implemented GDSII.

inFact
Wednesday, October 10 • 1:00pm – 2:00pm
Pete LaFauci, Application Engineer, Mentor Graphics

This presentation introduces the concept of algorithmic generation for functional verification. The discussion will cover the strengths and weakness of directed and random techniques, and why algorithmic generation introduces additional thoroughness and efficiency to the functional verification process. The inFact solution from Mentor will be described as an enabling technology. Attendees will learn how inFact can be integrated into existing verification methodologies. We recomment that verification, design engineers and design manager attend this session.

Catapult C: High Level Synthesis Technology
Wednesday, October 10 • 2:00pm – 3:00pm
Mike Bradley, Mentor Graphics

Catapult takes a C/C++ description of an algorithm and synthesizes it into hardware (RTL VHDL/Verilog).

By leveraging a high level language such as C/C++, developers are able to explore a vast range of implementation options. This is significantly faster than hand coding RTL. Synthesizable C code can then be used as a repository for technology indepent design IP (intellectual property).

The C code for Catapult is easier to write than RTL, since only the algorithm's functionality is described. Timing, FPGA/ASIC technology, and signal interfaces are created by the tool. Catapult allows the user to trade-off area vs. performance so that design goals are met. Different hardware architectures are obtained by synthesis directives and the datapath defined in the C code.

The technology within Catapult is targeted towards computationally intensive data algorithms such as: Wireless baseband processing, Image and Video processing, and various digital signal processing (DSP) algorithms.

Catapult is production proven with over 70 ASIC tape-outs and even more FPGA deployments. Real engineering teams are able to reduce their time to market and increase the number of design completions per year.

Please join us for a presentation and discussion of Catapult High Level Synthesis.

SystemVerilog for FPGA Designers
Wednesday, October 10 • 10:00am – 12:00pm
Ehab Mohsen, Technical Marketing Engineer, Mentor Graphics

Modern FPGAs have seen tremendous advances in both performance and capacity. With these increased capabilities, designers are faced with the daunting task of verifying and validating that their design intent is represented in the finished product. SystemVerilog provides a comprehensive language that is a natural extension of Verilog, with the benefits of providing constructs with clearer intent, enumerated types, integrated assertions for simulation and higher language constructs which support design hierarchy and Object Orientated Programming (OOP) styles.

Mentor Graphics' Precision® Synthesis provides the most complete SystemVerilog coverage of this language in FPGA synthesis. This easy-to-use tool empowers designers to utilize sophisticated RTL and physical optimization algorithms to clearly express their design intent.

B>Agenda

1. Introduction to effective design with SystemVerilog
   
2. Learn how to write fewer lines of code that actually do more
   
3. Mixing Verilog, VHDL and SystemVerilog in the same design
   

Who Should Attend: FPGA designers and team/project leaders targeting FPGAs

Introducing Mentor's Newest Addition to the Precision Synthesis Product Family
Wednesday, October 10 • 1:00pm – 2:00pm
Ehab Mohsen, Technical Marketing Engineer, Mentor Graphics

More information coming after product release

Mentor Graphics FPGA Design tools
Wednesday, October 10 • 2:00pm – 3:00pm
Dan Gardner, Technical Marketing Engineer, Mentor Graphics

This session will focus on emerging trends and issues in FPGA design, including discussion of how leading FPGA designers are overcoming various hurdles and what Mentor Graphics is doing to help. You'll learn about upcoming releases of Mentor Graphics software for FPGA design. This session will benefit all existing Mentor Graphics customers designing FPGAs or those designers just starting in FPGA by showing users the latest feature, flows and methodologies for FPGA design.

Keynote
Expedition
PADs
General
High-Speed
IC-ASIC
FPGA
Schedule (pdf)