General Topics
High-Speed PCB
PCB
FPGA
PADS
IC ASIC

General Topics

We all have heard the sales pitch for FLEXNet Manager, but what is the truth? I will compare and contrast FLEXNet Manager with SAMSuite/SAMReport based on real world experience. I will also cover what are the real benefits of investing in FLEXNet, as well as what we found that improved our lives, what surprised us and what made our lives more difficult.

The Mentor Graphics SupportNet web site is undergoing substantial improvement based on customer feedback collected from usability tests and surveys. This session will provide a preview of the new SupportNet which leverages a product profile for each user and a task-oriented design to speed the process of finding answers or researching features of Mentor Graphics tools.

The redesigned SupportNet site will be featured in the MARLUG usability lab.

Expedition WG2004 Service Pack 2 has joined the ranks of the Falcon framework by providing Design Automation functionality (A.K.A. UserWare). This paper will introduce users to Visual Basic 6.0 (VB6). The paper is intended for first time users of VB6. Bruce will cover VB6 environment, language syntax, File I/O, String Manipulation, Introduction to objects and creating procedures/functions.

This paper presumes the audience is familiar with VB6 programming. Bruce will look at the Expedition object structure, how to access the application, a design, obtain a license, and accessing data within a design. Finally, he will walk through a small sample program which demonstrates the usage of a form, extracting information from an Expedition database and populating the form with the extracted information.

Have you noticed that impromptu conversations at MARLUG can be as valuable as the sessions themselves? These meetings are a type of informal learning that will become more important to your job as time goes by. In fact, some companies are codifying informal knowledge networking (Communities of Practice) as critical conduits of information.

This session will explore the nature of informal learning, and present ways to increase both the speed and appropriateness of the knowledge you seek. Coming enhancements to Mentor Graphics products and services will be presented, (InfoHub, Video Whiteboards, On-Site Mentoring) along with a framework that brings learning to the worker instead of requiring the worker to go to the learning.

High-Speed PCB

This presentation covers methodology using Hyperlynx 7.5 for planning and verification of a complex high speed design. This version of Hyperlynx added several new features like via visualizer and free from schematic that were applied to analyze a 1.5GHz High Speed Data Acquisition PCB with 3.125GHz Rocket I/O. This presentation will discuss how LineSim was used to analyze the effects of via stubs on very fast rise time digital signals (50ps), and Rocket I/O. It will also discuss how the Rocket I/O design kit and Eldo Spice option were used to analyze and predict proper PCB structure to support these high speed interfaces, and how the PCB post rout layout was verified using Hyperlynx BoardSim PCB extraction tool.

With the paradigm shift from wide, parallel bus architectures to higher-speed, serial busses also comes a shift in design methodology. This presentation will examine the design concerns in SERDES channels, and investigate the analysis necessary to overcome those challenges. The capabilities of our design tools, from the earliest stages of the design cycle to post-route verification, will be utilized for demonstration of a successful implementation of a SERDES channel design.

This presentation will highlight the new features in HyperLynx 7.7. These include an updated and advanced scope, editable vias models in LineSim, fast eye diagrams, the Touchstone Viewer for S-parameters, S-parameter extraction, integration of the ADMS simulator, batch mode enhancements, improved IBIS support, and more! The presentation will go into detail on these updated features and will include a demo as well.

APL recently completed several complex high speed designs. This paper will describe the methodology used, including delay formulas, customizing topologies, matched lengths and tuning nets. We will describe how we used the hazards to find nets that were out of spec, and rule areas schemes to adjust track to track spacing near components.

PCB designers more and more are facing the high-speed design problems that increasing bus speeds, faster switching speeds, and clock speeds are causing in modern designs. In an easy to understand presentation we will discuss practical techniques you can use in routing high speed designs, and how by carefully managing layer definition, trace coupling, and route widths and lengths, you can avoid these problems.

The IBIS IC modeling specification has constantly been evolving to meet the changing needs of the industry. One of the latest, most dramatic additions has been in the IBIS 4.1 spec. This presentation will focus on the additions in the IBIS 4.1 specification and AMS modeling. The webinar will go through the evolution of the IBIS spec, and how AMS can meet modeling needs well into the future. Details on how SPICE models and AMS models are used in the IBIS format will be discussed. A brief overview of AMS modeling will also be included.

PCB

The new Board Station XE flow provides dramatic productivity improvements and industry-leading technology innovation for PCB designs. This session, targeted at current Board Station users, will demonstrate the power of the BSXE flow and how it leverages customers' investment in libraries, front-end tools, and legacy designs.

This session will review some of the new capabilities available in the 2005.1 release. Special attention will be given to areas such as XtremeAR, CES, DMS, layout and manufacturing prep. Also, a short term technology pipeline will be discussed highlighting some of the pending deliverables such as the Topology Router. A must see!

This presentation will show how to define and load new package types in “Package type clearance rules area, and how to load the package type-to-package type database. This presentation will also contain how to add this new package types in the library or design. This presentation will also show how this work on a design.

Manufacturing drawing preparation and documentation is a critical step of the PCB design process, providing detailed information for design, test fabrication, assembly, manufacturing and detailing ECOs. However, it is often over looked when planning and scheduling for PCB design. In this session, discover how the new FabLink XE Drawing File Editor coupled with Automation can significantly improve the quality and reduce the time taken to create your drawings and documentation which was typically a labor intensive operation. This will allow designers to spend more time doing just that and reduce the associated costs and overall design time without relaying on third party applications.

If you're working on an LMS to DMS transition, you'll undoubtedly find problems and inconsistencies with your library data. We discovered a number of problems in our LMS library - and some good DMS utilities and methods to fix them. This presentation will be a series of case studies covering real-life situations and solutions.

I/O Designer provides bi-directional integration, data management and the ability to perform concurrent design of your FPGA and PCB. Offering a huge time savings in pin assignments, FPGA symbol creation for the PCB schematic, I/O Designer reduces the time-consuming error prone barriers getting your FPGAs on to your PCB. In the session we will discuss recent examples of how I/O Designer has been used to reduce design cycle times.

In order to design with the latest hot technologies, an understanding of their requirements, as well as associated design concerns, are necessary when making design constraints. HyperLynx Technology Design Kits provide an overview of the bus specifications, real simulation examples that can be used to modify designs to meet those specifications, and constraints resulting from the simulation analysis. This presentation will review all of the different HyperLynx Technology Design Kits, including PCI-X, DDR and DDR2, SATA, and PCI Express.

FPGA

The Accellera VHDL-2006 revision effort is creating types and operators that implement fixed and floating point math for VHDL. This paper will be a detailed introduction to the new types and packages, and their use model. This is an updated version of the paper presented at User2User 2006 and MAPLD 2005.

Accellera finalized its VHDL-2006 effort at DAC 2006. This paper summarizes the new features released by this standard and also talks about what is coming in the next revision of the standard.

This session will focus on emerging trends and issues in FPGA design, including discussion of how leading FPGA designers are overcoming various hurdles and what Mentor Graphics is doing to help. You’ll learn about upcoming releases of Mentor Graphics software for FPGA design. This session will benefit all existing Mentor Graphics customers designing FPGAs or those designers just starting in FPGA by showing users the latest features, flows and methodologies for FPGA design.

Using a pseudo-random testbench to demonstrate compliance with the DO-254 standard starts with carefully planning of what and how we check. This paper will show how a testbench can take advantage of the features of the new System Verilog IEEE-1800 standard such as Object Oriented Programming, Functional Coverage, and Random stimulus generation while still clearly demonstrating DO-254 compliance in its testing. A VHDL design coupled to a System Verilog testbench will be demonstrated. Other subjects covered are; Formal verification, assertions, and the Unified Coverage Database.

The promise of IP is that it will save you time. Why reinvent a design that has been around forever? Just drop the IP into your new design and connect it up and move the product out the door faster. However, the paradox is that using IP can actually cause you to lose time, as you try to figure out what the IP does and if it works. In addition, you need a method to transfer this IP knowledge to others within your group or company, so that they too can use the IP quickly. This talk will introduce you to some new features in HDL Designer that solve the Paradox of IP Reuse and help you get your product out the door faster.

Precision Synthesis offers award-winning design analysis capability to quickly locate timing problems and design bottlenecks, discover their causes and implement solutions to accelerate time to market and effectively produce high-quality FPGA designs. This session demonstrates how designers can modify constraints, reapply them to a synthesized database and perform incremental timing analysis, all within an easy-to-use design analysis environment. Also discussed will be how Precision Synthesis improves designer productivity with a unique cross-probing capability between reports, schematics, and HDL source.

PADS

PADS users will not want to miss this session discussing new RF design functionality, alphanumeric pin support, and other new functionality planned for the upcoming PADS 2007 release.

Mentor offers a variety of free design and library translators that cover all three PCB design flows - Boardstation, Expedition, and PADS. Come to this session to see which translators are available for your design process.

IC-ASIC

Mixed Signal Via Configurable Arrays (MS-VCAs) are the new alternative to full-custom mixed signal ASIC design. MS-VCAs offer distinct advantages in lower tooling costs (< 1/10^th typically), faster development time without backend verification and affordable re-spins. As the name implies, a complete mixed signal device is defined by a single programmable VIA layer (PVL.) The creation of a PVL essentially follows the same flow as any front end design. That is, the digital section is captured in Verilog and synthesized using the VCA library. The analog portion is created by drawing a schematic using the VCA symbol library. The composite netlist (analog SPICE + Verilog) can then be simulated in ADVance MS. That is where the similarities end between MS-VCAs and full-custom. In the MS-VCA world there is no backend—you don’t have to do DRC and LVS.

In this presentation we will describe how a 2^nd order Sigma Delta Analog-to-Ditigal Converter (ΣΔADC) can be designed and simulated using the MS-VCA libraries. The methodology for doing mixed signal simulations using ADVance MS with the MS-VCA library will also be shown.

Talk about advanced verification methodologies and improved verification is sweeping the industry. Why? There are ASIC’s and IC that have more functionality and greater scope that need to be verified. Mistakes can be very costly, and every means possible should be considered for achieving the highest levels of coverage.

This paper addresses the aspects of processor-driven testbenches utilizing a co-simulation product from Mentor Graphics called Codelink-Pro. We will explore the idea of using the on-chip processor as an additional source of stimulus for better functional coverage. Verification engineers can leverage snippets of code written by the software team, to help explore additional state-space in their designs. Assertion Based Verification methodologies are augmented using this approach to look for assertion firings and hardware errors.

In today's IC design services market, tool cost remains a significant factor in the overall project budget. In order to stay competitive, opportunities for cost reduction must be continuously explored. It is necessary to make decisions on tooling that will lower the costs, but yet not sacrifice efficiency and/or accuracy. We present a mixed Windows/Linux design flow that makes use of two Mentor graphics tools, DXDesigner and Calibre, along with other tools for layout and simulation.

Hardware Verification with C++

Join authors Mike Mintz and Robert Ekendahl as they discuss their new book, "Hardware Verification with C++". This book covers Object Oriented Programming (OOP) in general as well as Teal, and Truss, their open source verification libraries. Mike and Robert will present a path to starting OOP as well as "lessons learned" from over 20 years of object oriented programming.

In addition, Bennet IH of SigmaTell, will discuss the verification system he implemented on top of Teal.

Teal is a tiny C++ library that makes interaction with Verilog virtually seamless. Truss is an open source C++ library that provides a flexible verification framework. Both of these libraries have been in proprietary use for several years.

Design or Verification Engineers interested learning more about C++ and OOP in general should attend.

Just as eggs, milk and flour will only make a mess in your kitchen without the right recipe, you can't build an effective verification environment without the right methodology. This session will introduce Mentor's Advanced Verification Methodology (AVM), which uses a "cookbook" approach to show you how to build reusable transaction-level testbenches in SystemVerilog and/or SystemC, that let you apply such leading-edge techniques as constrained-random simulation, functional coverage and assertions in a practical and straightforward manner. If you're wondering why it is that you've been hearing about these techniques for years, but no one's been able to show you how to apply them to your particular problem, it's because no one has been able to deliver a powerful yet easy-to-adopt methodology to handle the difficult issues of testbench architecture, modularity, and communication. Until the AVM, that is. Come and let us show you how to verify your design at multiple levels of abstraction while effectively measuring your progress and finding more bugs than you ever thought possible.

This session will cover two topics. Traditional mixed-signal post-layout flow combines ASIC and analog flows, but requires significant manual work that is slow and error prone. Calibre xRC GUI-driven mixed-signal extraction automates the flow. We will overview this single step extraction and netlisting capability using Calibre Interactive and Calibre xRC. The second topic is simulation of mixed signal circuits. Large mixed-signal system-on-chip designs, blending complex analog and digital blocks, require thorough testing with the right mixed-signal verification tool. The ADVance MS mixed-signal simulator offers comprehensive technologies that support multiple modeling languages: VHDL, Verilog, VHDL-AMS, Verilog-AMS, SystemC, SystemVerilog, and SPICE. This session will also overview Mentor Graphics mixed signal simulation capabilities using ADVance MS.

General Topics
High-Speed PCB
PCB
FPGA
PADS
IC ASIC