High-Speed Design
Board Station / Expedition
FPGA
PADS
Design Environment
Functional Verification

High-Speed Design

In today’s high speed design environment, simulation tools must be used to guarantee first pass design success. Simulation tools can be used to verify performance of not only individual cards, but also complex systems comprising of a backplane and multiple plug in cards. This paper takes a look at using simulation techniques to find optimum design guidelines for designing a high speed backplane that meets signal integrity and timing constraints. It shows how various slot configurations can be compared to find design margins. Plug in card and connector models are used to provide simulation results that mirror reality. The paper also provides examples of lab measurements taken to compare the accuracy of the simulations to the real world.

Methodology using Hyperlynx 7.5 for Planning and Verification of a Complex High Speed Design. The latest Hyperlynx version added several new features like the via visualizer and free form schematic capture that were utilized at Northrop Grumman on a 1.5GHz Sample Data PCb with 2.1GHz Rocket I/O. This paper will discuss how the Linesim was used to determine the proper via structure (blind/buried vs through hole) for very fast rise time digital signals (50ps), and Rocket I/O, how the Rocket IO design kit and Eldo Spice option were used in pre rout simulations to predict proper PCB structure, and finally how post design layout was verified by extracting the PCB data to Boardsim.

Alexander James Golian is a Senior Electrical Engineer for Northrop Grumman Corporation and a Graduate of NCSU: BSEE, and Johns Hopkins University: MSEE High Speed Digital/Analog PCB Designer

High-speed memory subsystems, such as Double Data Rate (DDR) memory that is commonly used in Computers, Networking, Telecommunications, Consumer Electronics, Military, and Automotive applications - sustain the high-bandwidth needs of today's products. As processor and transmit speeds continue to increase, it becomes increasingly difficult to meet timing and signal integrity requirements on these interfaces. This presentation will cover DDR technology, common design issues, and layout constraint development for the interface using HyperLynx LineSim.

This session will present an overview of the 2005 and beyond product strategy for PCB high-speed design tools. It will include new features and products. Design verification with high-speed tools has become a critical consideration as IC manufacturers continue to release products on smaller dies with faster switching. This session is a "must see" for anyone designing circuits with modern chips.

Kevin Cohan is a product marketing manager for Mentor's Systems Design Division, focusing on design and verification products for high-speed boards. He has been in the EDA industry since 1994, working primarily in the area of timing and signal integrity analysis and verification. He holds a BSEE from Clarkson University, and an MSEE from University of Massachusetts, Lowell.

Board Station / Expedition

The new Mentor product that is certain to become a "strong competitor" in the ECAD Design Tool market is Advanced Technology (also known as,the SuperMax ECAD Tool!) This Tool is an "excellent new version" of the existing SuperMax product developed in Europe. Acquired by Mentor within the past few years, this product has ,in a very short time frame, become an extraordinary RF/MCM {Multi-Chip-Module} design product. A product that has been "sorely" needed in the industry, as only a "few" Companies had the "tailored software" that is required for complex/cutting edge Multi-Layer Ltcc [Low Temperature Co-fired Ceramic], Htcc [High Temperature Co-fired Ceramic] and RF Tile/Manifold designs. SuperMax has many extraordinary features that are not usually available in standard PCB Tools:

Timothy L. Eder is an Electro-Mechanical Designer with over 20 years of progressively responsible experience in mechanical design and drafting with Westinghouse, ESG and Northrop Grumman, ESSS. Recipient of a patent and trade secret award in 2001.

Unresolved dimensions, a form of database corruption, have been an ongoing fact of life for all BoardStation users. In 1996, a freeware alternative called flat dimensioning was offered to the userbase as a proven methodology for preventing new occurences of unresolved dimensions. This presentation will discuss the principles of flat dimensioning, and offer an additional freeware solution to finally eliminate all existing unresolved dimensions.

Al Wainwright implements ECAD engineering solutions for L-3 Communication Systems - East in Camden, NJ. He has worked in circuit design automation engineering for the past 31 years, and received the Scott Jeffreys Award at MUG/User2User 2004.

Mentor's tool acquistions over the last few years have presented users with a number of choices for schematic capture and board layout tools. Many companies now find themselves supporting multiple schematic and layout tools with limited staff and resources.

After reviewing many tools and process flows, we at Northrop Grumman have standardized our board design process to use one schematic tool - Design Architect - to drive three board layout tools - BoardStation, Expedition, and Supermax. This presentation will present our process flow and share problems and challenges we face in implementing and supporting this flow at multiple sites.

Kelli Hosier supports Ecad applications and Unix workstations at Northrop Grumman in Baltimore, MD.

This presentation reports on the current state and future plans of the Board Station products, highlighting new products and key features added to Board Station and BSRE in the EN2004 releases like those that embrace advanced technologies like Embedded Capacitors/Resistors and Flex, as well as those new products and flows planned for the near future. This presentation will also discuss current activities aimed at increasing performance in the areas of Routing, area fill & planes processing and BSRE adoption (I.E. pin & gate swapping, testpoints, etc.).

This presentation is meant to show Mentor Graphics is continuing to invest in Board Station to continue to provide customers access to leading edge technology, allowing the customer to leverage his current investment in processes, tools, libraries, data and flow.

A 20 year veteran of Mentor Graphics, Philippe Bridenne is currently the Director of Product Marketing for the Board Station RE Product line, which includes the following products:

What's New in Expedition Enterprise – Expanding Your Horizon
Charles Pfeil
Mentor Graphics

This presentation reports on the current state and future plans of the Expedition PCB flow, highlighting new products and key features added to the Expedition PCB tool and the Expedition Enterprise flow in the EXP2005 release. There are significant enhancements in constraint management, flex design, high speed design, autorouting and fabrication tools.

This presentation will also discuss current activities aimed at increasing performance in the areas of routing, area fill & planes processing.

This presentation is meant to show Mentor Graphics is continuing to invest in the Expedition flow, allowing customers to increase productivity and address new technologies.

A 12 year veteran of Mentor Graphics and with over 30 years in the PCB industry, Charles Pfeil is currently a Director of Engineering for the Expedition PCB product.

FPGA

As Integrated Circuit (IC) geometries and core voltages decrease, the probability of incurring system faults increases significantly. The most common types of errors that can occur within terrestrial systems are Single Event Upsets (SEUs) and Single Event Transients (SETs). SEUs and SETs can occur when ions or photons traverse device areas and are capable of creating electron-hole pairs in semiconductor materials (also referred to as Directly Ionizing Events DIEs)). This paper will address the pros and cons of common mitigation design techniques utilized to correct possible SRAM Based FPGA device malfunction due to terrestrial DIEs. A discussion of synthesis solutions will also be presented.

This session will focus on emerging trends and issues in FPGA design, including discussion of how leading FPGA designers are overcoming various hurdles. You’ll learn about upcoming releases of Mentor Graphics software for FPGA design. This session will benefit all existing Mentor Graphics customers designing FPGAs or those designers just starting in FPGA design. New features and support planned for 2005 will be covered to help with today’s leading FPGA devices using the latest flows and methodologies.

Modern FPGA technology, with tremendous advances in both performance and capacity, is now a very viable solution for many high performance designs. Not only are FPGAs popularly used to minimize risks in both schedule and costs but also for their flexibility to accept design modifications during the product life cycle. Design methodologies must be tailored to confront the obstacles presented by these multi-million gate FPGA designs. These obstacles in addition to meeting design requirements include support for complex design flows, advanced language compatibility, and productivity enhancements.

Synchronous Design Techniques for Reliable Circuitry
Melanie Berg
NASA GSFC

It has been proven that as the amount of functionality placed within an ASIC or FPGA increases, the complexity of the design grows exponentially. The ability to create reliable circuits has become an incredibly difficult task. This session will discuss specific Synchronous Design Methodologies that enhance the reliability of ASIC/FPGA circuitry. Topics covered will include, Design for Verification, Synchronizing multiple clock domains, Handling of I/O, and Synchronous vs. Asynchronous circuitry. Participants will receive hands on tutorials of design flow including ModelSim, Precision Synthesis and design analysis techniques.

PADS

As the dominant name in desktop-based PCB design, PADS 2005 continues a tradition of solid technical excellence and innovation. Come to this session to see what new functionality has been introduced to PADS in 2005, and what's is store for 2006.

By now, you’ve probably heard about the upcoming hazardous materials regulations that various countries are implementing to make our industry more environmentally conscious. Commonly referred to by acronyms such as WEEE and RoHS, these regulations mean big changes for the electronics industry. Come to this seminar to understand how Mentor can help you prepare for these regulations.

The speaker will review the signaling requirements for Rocket I/O and show how the Rocket I/O Technology kit from Hyperlynx can be used to verify your implementation of this SERDES interface.

Ernie Frohring is a Senior Applications Engineer with 11 years of experience helping customers implement high speed designs. He has a BSEE and MSEE from MIT University.

The speaker will give an overview of ROHS and WEEE requirements, and show how using DX Databook you can access ROHS compliance information, managed by Omnify PLM, directly from DX Designer. Also, Chuck will review ROHS documentation requirements and how to produce the documentation set required to prove compliance when audited.

Chuck McGinley has over 15 years experience with DX Designer. For the last 4 years Chuck has also been implementing Omnify PLM Systems integrated with DX Designer to help customers manage component, BOM, documentation and change processes, and integrate the design process with enterprise business systems.

Design Environment

You've probably heard about Mentor's Data Management System (DMS), and have wondered how you can take advantage of this powerful environment. Mentor's library and design management tool can be complex, as well as challenging to implement. This presentation is your opportunity to learn from the real-life experiences of our still-in-progress LMS to DMS transition. Find out how to handle:

This is your opportunity to see how DMS can become a valuable part of your design process.

Phil Lindberg is part of the Design Automation support organization within the Johns Hopkins University Applied Physics Lab's Technical Services Department.

Expedition WG2004 Service Pack 2 has joined the ranks of the Falcon framework by providing Design Automation functionality (A.K.A. UserWare). There are a variety of languages which are supported in the Design Automation environment. This paper will look at utilizing Visual Basic 6.0 (VB6) for access to the Expedition and DxDesigner database. The paper is intended for first time users of VB6. Bruce will define some of the frequently used terminology in Object Oriented programming and how it apply to the access of Expedition & DxDesigner. The next step is to write some userware.

Bruce currently holds the position of Manager, Electrical Design Automation for Northrop Grumman, located outside Baltimore, Maryland. Bruce has been actively involved in the PCB design industry since 1979 utilizing a myriad of tools. He holds a Bachelor of Science degree in Computer and Information Systems.

Mentor Graphics is deploying a new mechanism for installing its software, and several products are using the new installer today. The installer’s GUI and functionality are the same across all platforms, and is intended to be a user-friendly application that assists users through the installation process. This session introduces the new installer and describes its features. It discusses the ways the new installer helps maintain the integrity of customer sites by guiding the user through the installation process. It also discusses some of the features the new installer provides beyond installation of software. The session concludes with the vision of the future for the new installer.

Jim has been developing software for 20 years and currently works in the Install and Licensing Software group. He is one of the lead architects and developers of Mentor Graphics’ new installation mechanism. Jim specializes in Graphical User Interface design and has a M S C S from the University of Alabama in Huntsville.

Adopting a new platform is always a challenge, and Linux is no exception. You must consider the roll-out of the hardware and OS in addition to the design tools. A great deal of groundwork must be done to determine if the platform is a good fit for the tools you intend to run. Licensing, printing and the user environment must also be considered. With so many unknowns, where do you start? This session is intended to provide guidance for those who are considering a Linux environment for use with the Mentor Graphics suite of board design products. Hardware and OS requirements, deployment strategies, the Mentor Graphics license and printing environment and the user environment are presented along with practical examples to help you get started.

Ken Foster is an environment support CAE with Mentor Graphics Corporation with over 20 years of system administrator experience supporting a variety of UNIX, Linux and Windows platforms.

Functional Verification

Advanced verification techniques and self-checking testbenches are essential for debugging today's 10M gate FPGAs. This paper shows you how to create a self checking testbench in HDS. This testbench includes transaction level verification, assertion based verification, functional coverage, and a self-checking scoreboard. Engineers who employ this style of testbench will find that their time in the lab is considerably shortened and that they can deliver to schedule more reliably.

Ray Salemi is a HDL Designer Series Technical Marketing Engineer. Ray is a 15-year veteran of the functional verification industry and FPGA Design.

Functional errors in electronics for avionics systems may have severe consequences as human lives depend on the proper functioning of the aircraft electronics. To ensure the highest quality and to achieve the goal of zero functional bugs in these quality-critical systems, Thales Airborne Systems is taking a new approach to FPGA design verification. Based on recent support for a standard property specification language (Accellera’s PSL), Thales Airborne Systems is incorporating assertion-based verification (ABV) using with PSL. This paper will discuss our results in evaluating ABV methodology, PSL and commercial EDA software supporting ABV.

This paper will address our reasons for investigating hierarchical test benches and describe some of the techniques we have developed for incorporating this methodology in our FPGA design flow at APL.

Mary Harris works for the Johns Hopkins University Applied Physics Laboratory as a member of the EDA tool support staff responsible for design and verification methodologies of FPGA-based designs. Mary received a B.S.E.E. from the University of Maryland and a M.S.E.E. from Johns Hopkins University.

Eliminate clock-domain crossing errors in RTL with “0-In CDC”
Chris Rockwood
Mentor Graphics

Faulty management of clock-domain crossing (CDC) signals is a major cause of functional errors in silicon. In this session, we examine how to use the 0-In CDC product to identify potential CDC problems early in the design cycle. We explore using a mix of advanced technologies, which include the innovative CDC-FX metastability analysis system.

Mr. Rockwood has nearly 20 years of experience in engineering design, customer support and marketing. Prior to Mentor/0-In, Mr. Rockwood worked for several companies as an ASIC/FPGA designer, including Apple Computer, Motorola and Ardent Computer, where he was one of the first users of synthesizable Verilog and Synopsys Design Compiler in the late 1980s. Mr. Rockwood holds a B.S. in Electrical Engineering from Rice University in Houston, Texas.