| 2005 MARLUG Conference |
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| Thursday, Oct.
6th |
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| 8:00 |
Registration and Continental Breakfast |
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| 8:45 |
Welcome and Announcements - MARLUG Chair |
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RMS 1 & 2 |
RMS 3 & 4 |
RM 5 |
RM 6 |
RM 7 |
RM 8 |
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Dining Area |
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PADS |
Board
St / Expedition |
High-Speed |
FPGA |
Functional
Verification |
Design
Env |
Custom IC |
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| 9:00 - 10:00 |
Simulating Xilinx
Rocket I/O With Hyperlynx GHz |
SuperMax ECAD Tool |
Using Simulation
Techniques to Guarantee Successful Backplane Design |
Single Event Upset Design
Techniques for SRAM Based FPGA Devices |
Advanced Verification with HDL
Designer Series |
DMS
Essentials: Learning From APL's LMS
to DMS Adventure |
Session 1 |
What's
New in Expedition Enterprise – Expanding Your Horizon |
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| Ernie Frohring |
Timothy Eder |
Johnnie Osborne |
Melanie Berg |
Ray Salemi |
Phil Lindberg |
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Charles Pfeil |
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| Trilogic |
Northrop |
NASA GSFC |
NASA GSFC |
Mentor |
JHU / APL |
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Mentor |
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| 10:15 - 11:15 |
Using DX Designer & Omnify PLM
to Manage ROHS Information |
All Dimensions Resolved!! |
Methodology
using Hyperlynx 7.5 for Planning and Verification |
Mentor FPGA Design Tools |
Assertion-Based
Verification with PSL for Quality-Critical Electronic Systems |
Welcome
to VB for Expedition Automation & DxDesigner |
Session 2 |
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| Chuck
McGinley |
Al Wainwright Jr. |
Alex Golian |
Dan Gardner |
Raghu Ardeishar |
Bruce Mayer |
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| Trilogic |
L-3 Comm |
Northrop |
Mentor |
Mentor |
Northrop |
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| 11:30 - 1:30 |
Lunch |
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| 1:30 - 2:30 |
RoHS Compliance: What Engineers
& PCB Designers Need To Know |
To_Layout and
Beyond - A Tool Story |
High-Speed
Update |
Synchronous Design Techniques for
Reliable Circuitry |
Hierarchical Test
Benches |
Mentor Graphics New
Installation Mechanism |
Session 3 |
What's
New in Expedition Enterprise – Expanding Your Horizon |
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| Jim Oakley |
Kelli Hosier |
Steve McKinney |
Melanie Berg |
Mary Harris |
Jim Luick |
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Charles Pfeil |
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| Mentor |
Northrop |
Mentor |
NASA GSFC |
JHU / APL |
Mentor |
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Mentor |
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| 2:30 - 3:30 |
PADS Product
Update |
What's
New In Board Station RE - |
DDR
Technology with HyperLynx |
Precision Synthesis
-- Advanced Synthesis for Complex FPGAs |
Eliminate
clock-domain crossing errors in RTL with “0-In CDC” |
Getting started
with Mentor Graphics board tools on Linux |
Roadmap |
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| Jim Oakley |
Philippe Bridenne |
Steve McKinney |
Dan Gardner |
Chris Rockwood |
Ken Foster |
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| Mentor |
Mentor |
Mentor |
Mentor |
Mentor |
Mentor |
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| 3:30 - 4:00 |
MARLUG Business Meeting |
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| 4 - 6 |
Reception |
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| 9 -
4 |
Mentor Graphics' Usability Lab -
Room 9 |
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| 10 -
6 |
Vendor Fair |
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