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MARLUG 2004 Proceedings Listed below are papers and presentation from the 2004 MARLUG annual conference, with links to each document. Please note that some web browsers have problems displaying large presentations. You may wish to save the document to your local hard drive and open it directly. Mentor Graphics Roadmap presentations are considered proprietary information and are not released for publication. FPGA Implementing Rule Checking Early in the Design Cycle to Reduce Design
Iterations and Verification Time Integrated System Design: A Focus on FPGA I/O Design FPGA/PCB Verifying Actel Paths using Microsoft Excel A Printed Circuit Board Design with HDL Designer General Adding a Graphical User Interface to Windows K-Shell Scripts Real-Life LMS to DMS Migration: Rubber Meets the Road Library Component Data Obsolescence Management, Meet & Exceed Product
Lifecycles Ideas to Simplify a Remote Xserver Environment General PCB Schematic Re-use 101 using Managed Hierarchy Xtreme PCB - New PCB Design Solution High Speed A Signal Integrity Simulation Case Study on Space Flight Hardware
Prototypes Real World Termination Dilemmas and solutions Using Innovative Tool Capabilities in ICX to Your Advantage Using Hyperlynx to Reduce Risk in Hi-Speed Designs Checking Vendor IBIS Models Using Hyperlynx Visual IBIS Editor PADS Using PADS Router in a PCB Design Flow PADS Router Basics Using PowerPCB to Drive SMT Assembly PCB Fix EMI Problems using Quiet Expert Dissection and Execution of Automation Scripting for ExpeditionPCB For the demonstration VBS scripts referenced above to execute correctly, they must be run on a system with a licensed ExpeditionPCB and Automation environment, while an ExpeditionPCB design file is open. Terry Lovell's material also includes: Animation (Real Player required) Model Plot PointsArray Supermax ECAD PCB Design-for-Test Boundary Scan Design for Test Simulation Design of a Mixed Signal Multiplier Verification PSL What Is It, And How To Leverage It Today Tips and Tricks for Debugging ModelSim Issues Reducing HDL Design Verification Time Through The Use of Assertions and
3rd Party Simulation Models Accelerating Verification Through Pre-Use of System Level VHDL-200X: New Features Being Standardized
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