MUG 2001/2002 Agenda

Sunday, February 24
Monday, February 25
Tuesday, February 26
Wednesday, February 27

Sunday, February 24
	Time	Program
	11:00am-6:00pm	CONFERENCE REGISTRATION
	1:00-5:00 pm	Workshops: High-Speed Board Design Workshop FPGA Advantage - A complete design flow solution for multi-million gate FPGA design
	5:00-7:00 pm	Welcome Reception
	7:00-9:00 pm	Steering Committee Meeting
Monday, February 25
	Time	Program
	7:30-9:00 am	Speaker Breakfast
	7:30-9:00 am	Breakfast
	9:00-9:15 am	Opening Remarks David Zar
	9:15-9:45 am	Mentor Graphics Welcome Wally Rhines
	9:45-10:15 am	Customer Support Update Tom Floodeen
	10:15-10:30 am	MUG Appreciation Awards
	10:30-10:45 am	Break
	10:45-11:45 am	Keynote Speaker: Bob Colwell, Independent Consultant Title: Microprocessor War Stories
	11:45am-12:45pm	Analog_Sim SIG Meeting
	11:45am-12:45pm	University SIG Lunch Meeting
	11:45am-12:45pm	RF SIG Meeting
	11:45am-12:45pm	Lunch
		Design Support	PCB Design1	PCB Design2	Circuit & System Design
	12:45-2:15 pm	9. Automatic FPGA Mapping - Kodak - 30 mins 6. Putting the (Mentor) User in Usability - Mentor - 30 mins	What's New & Cool with Board Station RE - 30 min (new user) & 30 mins (expert user)	What's New and Different in WG2000.5 - 60 mins	2. Accurate Simulation of Mosfet - Signal Processing - 20 mins
	12:45-2:15 pm	5. Pick it Click it, Get Information - Mentor - 30 mins	52. Using Variants in PCB Designs - Honeywell - 30 mins	59. FPGA on Board - Mentor - 45 mins	58. Configuration of Extraction Deck for an N-Well CMOS Process - Duke University - 20 mins 53. Developing Applications in Power Electronics - PUC Mines - 20 mins
	2:15-2:45 pm	Break
		Design Support	PCB Design1	PCB Design2	Circuit & System Design
	2:45-3:45 pm	Library SIG Meeting	15. Calculating Component Area Reqs. - Mentor - 30 mins 32. Finding a Needle in the Haystack - QCP - 20 mins	60. Key-In Commands for Expedition and Rule Areas - Mentor - 60 mins	IC Q&A and BOF
	3:45-4:00 pm	Break
		Design Support	PCB Design1	PCB Design2	Circuit & System Design
	4:00-5:30 pm	31. Using WorkXpert - Litton - 30 mins 21. A Few ExAmple Concepts - Lockheed Martin - 30 mins	18. Front End Board Design Panel - Mentor - 90-120 mins	41. WG2000.05 Out of the Box - Loading the Software and System Setup - 90 mins	4. A comparison of Two VHDL Memory Modeling Techniques - Acuson - 20 mins 35. Animation of a VHDL Model using ModelSim - U of Missouri - 20 mins 36. A New Technique for Modeling - Mentor - 20 mins 42. Library Verification - Mentor - 20 mins
	5:30-6:30 pm		PCB SIG Meeting - 30+ mins	VBUG Business Meeting
	6:30-10:00 pm	Dave and Busters - Evening Activity - Complimentary Bus Transportation
Tuesday, February 26
	Time	Program
	7:30-9:00 am	Breakfast
	7:30-9:00 am	62. Userware SIG Meeting (Breakfast)
	7:30-9:00 am	License SIG Meeting (Breakfast)
		Design Support	PCB Design1	PCB Design2	Circuit & System Design
	9:00-10:30 am	Design Env Q&A - 45 mins Design Environment SIG - 45 mins	25. Interfacing Exp PCB to Harness - Micromass - 20 mins 14. Lcable - Embraer - 20 mins 33. Wire harness Design - Mentor - 45 mins	46. Cooking Show - Getting started/FPGAs - 30 mins 12. DXF & IDF Import & Export - Sercel - 25-30 mins 55. Expedition Library Manager Glitches & Workarounds - Optimum Design Assoc. - 30 mins	1. New Technique for Fast Number Comparison - Wayne State - 20 mins 3. Modulo RNS Arithmetic Adder & Multiplier Implementation - Wayne State - 20 mins 10. An ASIC Application of the RSA Algorithm - Hacettepe Univ. - 20 mins
	10:30-10:45 am	Break
		Design Support	PCB Design1	PCB Design2	Circuit & System Design
	10:45am-12:15pm	22. Putting FlexLM Report Logs to work - Honeywell - 20 mins 26. Managing Design Automation Licensing in SAMsuite - APL/Northrop - 30 mins	56. Generating a PDF w/ Searchable Text from a Board Station Layout - Lockheed - 30 mins 57. Engineering & Manufacturing Collaboration in the 21st Century - e4eNet - 30 mins	47. Cooking Show - Design Capture/Libraries - 30 mins Expedition SIG Meetings - Exp_Lib, Exp_DC, Exp_PCB	ASIC/FPGA SIG and Exp_FPGA SIG Meeting
	12:15-4:00 pm	Tradeshow (lunch included)
	4:00-5:30 pm	PCB Roadmap
	5:30-6:30 pm	Special Meeting - MUG Incorporation
	6:30-10:00 pm	Denver LoDo (Lower Downtown District) - Evening Activity - Complimentary Bus Transportation
Wednesday, February 27
	Time	Program
	7:30-8:30 am	Breakfast
	7:30-8:30 am	Workflow SIG Meeting (Breakfast)
	7:30-8:30 am	Cable SIG Meeting (Breakfast)
	8:30-9:30 am	MUG Business Meeting
	9:30-9:45 am	Break
		Design Support	PCB Design1	PCB Design2	Circuit & System Design
	9:45-10:45 am	16. Project Priority Mgmnt w/ModelSim & LSF - Platform Computing - 30 mins 44. Displaying the Interface of a Remotely-Run Tool on Linux - Mentor - 20 mins	61. How HDI Can Lower Board Costs, Improve TTM and Electrical Performance - Westwood Associates - 60 mins		ASIC/FPGA Roadmap with Q&A
	10:45-11:00 am	Break
		Design Support	PCB Design1	PCB Design2	Circuit & System Design
	11:00am-12:00pm	45. Vision for Linux in EDA - Panel discussion - Sun, HP & Mentor	30. A comparison of IS simulations - Hughes/Mentor - 30 mins 28. Library Migration - Mentor Classic Structure to Expedition Library Structure - Sandia National Labs - 30 mins	29. Zero to Boards in 6.8 Weeks - AirPrime - 30 mins 38. BGA Design Using Expedition - Intel/Sercel - 30 mins	17. Designing an Interconnection Network Test Bed - U of Alabama - 20 mins 40. What About the Little Ones - HEP, U of Illinois - 30 mins
	12:00-1:00 pm	Lunch
	12:00-1:00 pm	SIG Officers Lunch
		Design Support	PCB Design1	PCB Design2	Circuit & System Design
	1:00-2:00 pm	23. An Implementation of Concurrent Engineering - AMD - 20 mins 20. Process and Tools Training - Northrop - 30-45 mins	PCB Executive Q&A		63. FPGA Advantage - Design creation, management, simulation & synthesis in one complete flow - Mentor - 60 mins
	2:00-2:15 pm	Break
	2:15-3:15 pm	8. Electronic Model Attachment - Kodak - 30 mins 37. Fixing the "Split" Symbol Problem & other Nifty QuickSim/QuickSim Pro Enhancements - Mentor - 30 mins	Library & Data Management Session - Mentor - 60 mins		51. Powerful, Intuitive Synthesis for FPGA Design - Mentor - 60 mins
	3:15-3:45 pm	Break
	3:45-4:45 pm	50. O/S Forum - APL and Mentor - 60 mins	PCB Userware Future - Mentor - 60 mins	48. Cooking Show - PCB - 30 mins 49. Cooking Show - End game - 30 mins
	4:45-6:00 pm	Closing Happy Hour

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