All abstracts submitted to date are available for your review. You can review them individually by title or click here to review all abstracts.
| #1 |
A New Technique for Fast Number Comparison in the Resideu Number System Based on Chinese Remainder Theorem II |
| #2 |
Accurate Simulation of MOSFET Parasitics in a DA/Accusim Environment |
| #3 |
Modulo RNS Arithmetic Adder and Multiplier Implementation |
| #4 |
A Comparison of Two VHDL Memory Modeling Techniques |
| #5 |
Pick It, Click It, Get Information |
| #6 |
Putting the (Mentor) User in Usability |
| #8 |
Electronic Model Attachement |
| #9 |
Automatic FPGA Mapping |
| #10 |
An ASIC Application of the RSA Algorithm |
| #12 |
DXF and IDF Import and Export |
| #14 |
Lcable Add Connector/Component by Ref Performance Problems in House Solutions and Customizations |
| #15 |
Calculating Component Area Requirements |
| #16 |
Project Priority Management with ModelSim and Platform's LSF License Maximizer |
| #17 |
Designing an Interconnection Network Test Bed |
| #18 |
Front End Board Design |
| #20 |
Process and Tools Training: Establishing a Broad Base |
| #21 |
A Few ExAmple Concepts |
| #22 |
Putting FlexLM reportlogs to work for you |
| #23 |
An Implementation of Concurrent Engineering |
| #25 |
Interfacing Expedition PCB to Capital Harness Software |
| #26 |
Managing Design Automation Licensing using SAMsuite and the Web |
| #28 |
Classic Library to Expedition Library Conversion |
| #29 |
Zero to Boards in 6.8 Weeks |
| #30 |
A comparison of IS simulations vs. measured lab results in the Common Hub Modules Designed at the Mobile Satellite Systems Division of Hughes Network Systems |
| #31 |
Using WorkXpert for problem solving and library data control |
| #32 |
Finding a Needle in the Haystack - Design-Wide Searches in Design Architect |
| #33 |
Wire Harness Design and Manufacturing |
| #35 |
Animation of a VHDL Model in Modelsim Using Tcl/Tk |
| #36 |
A New Technique for Modeling Special Power MOSFET |
| #37 |
Fixing the "Split" Symbol Problem and Other Nifty QuickSim/QuickSim Pro Enhancements |
| #38 |
BGA Design Using Expedition |
| #40 |
But What About the Little Ones? |
| #41 |
WG2000.05, Out of the Box |
| #42 |
ASIC Library Verification |
| #44 |
On Displaying the Interface of a Remotely-Run Tool on Linux |
| #45 |
Vision for Linux in EDA |
| #46 |
Cooking Show - Getting Started with FPGAS |
| #47 |
Cooking Show - Design Capture/Libraries |
| #48 |
Cooking Show - PCB |
| #49 |
Cooking Show - End Game |
| #50 |
O/S Forum |
| #51 |
Powerful, Intuitive Synthesis for FPGA Design |
| #52 |
Using Variants in PCB Designs |
| #53 |
Developing Applications in Power Electronics: Automotive Systems |
| #55 |
Expedition Library Manager Glitches & Workarounds |
| #56 |
Generating a PDF with Searchable Text from a Board Station Layout |
| #57 |
Engineering and Manufacturing Collaboration in the Twenty-First Century |
| #58 |
Configuration of Extraction Deck for an N-Well CMOS Process |
| #59 |
FPGA on Board |
| #63 |
FPGA Advantage - Design creation, management, simulation & synthesis in one complete flow |
| N/A |
What’s New and Cool with Board Station RE |
| N/A |
What’s New and Different in WG2000.5 |