MUG 2001/2002 Abstracts

Title: A New Technique for Fast Number Comparison in the Residue Number System Based on Chinese Remainder Theorem II
Authors: Eid Al-Radadi and Pepe Siy
Org: Department of Electrical and Computer Engineering Wayne State University, Detroit, MI 48202
Email: ab1000@wayne.edu and psiy@ece.eng.wayne.edu
Phone: 313-577-8846

Abstract:
The residue number systems (RNS) have found application in digital signal processing. The main advantage of RNS is the carry free operation in addition, subtraction and multiplication. The parallel property of the RNS makes the addition, subtraction, and multiplication on long numbers operates at the same speed as on short numbers.

Due to the non-position nature of RNS, the comparison between RNS numbers is not as simple as in weighted number systems. The traditional techniques for RNS number comparison use the Chinese Remainder Theorem (CRT) or the Mixed Radix Conversion (MRC) [2]. A direct implementation of the CRT is inefficient and time consuming. The MRC is a complex sequential process, which causes long delay.

In this paper a new comparison algorithm in residue number system for new 4-moduli set is presented. This technique is faster than most competitive published works, based on MRC or CRT. The CRT requires large modulo M and is therefore costly to implement. The mixed radix conversion (MRC) is sequential process, which causes long delay. The proposed algorithm is based on CRT II.

The implementations of the algorithms were written using VHDL codes behavioral models or structural architectures and simulated by using Mentor Graphics' Modelsim. The codes synthesized using Exemplar's Leonardo Spectrum with the use of ADK (ASIC Design Kit) cells library, provided by Mentor Graphics Higher Education Program. The simulation of the circuit used Quicksim simulator, which capable of incorporating delays in the simulation.

Bio:
Eid Al-Radadi is a PhD student at Wayne State University in Detroit, Michigan. His research interests in computer architecture and VLSI designs. He received his BSEE from University of Detroit Mercy and his MSEE from Wayne State University.

Pepe Siy is an associate professor in the Electrical and Computer Engineering department at Wayne State University. His research interests are in the areas of VLSI, Residue Number Systems architecture, and Image Processing. He received his BSEE from Mapua Institute of Technology, Philippines, his MSEE at University of California, Berkeley, and Ph.D. at the University of Akron.

Title: Accurate Simulation of MOSFET Parasitics in a DA/Accusim Environment
Author: Joseph A. LeBritton
Org: Signal Processing Technologies, 4755 Forge Road, Colorado Springs, CO 80907
Email: lebritton@spt.com
Phone: 719-528-2224
Fax: 719-528-2375

Time Required: 20 minutes

Abstract:
In the design of very high speed analog integrated circuits, it is crucial that the parasitic capacitance and resistance of source/drain regions of MOSFET devices be modeled accurately. Accusim, like most SPICE-type analog simulators, assumes that each MOSFET contains a single gate stripe, and calculates the source/drain parasitics accordingly. However, for a MOSFET folded into a multiple-stripe device, this calculation is no longer accurate and can result in incorrect simulation results for high speed circuits.

SPT has resolved this problem by defining the number of gate stripes as a property on the DA MOSFET symbol. This provides an "ample" program with sufficient information to accurately calculate the MOSFET parasitics, which is then automatically fed to the Accusim netlister for simulation. The new gate stripes property also assists users of ICStation when generating, folding, and placing these devices.

Mentor Products: Design Archictect, Accusim, ICDevice, ICGraph, Ample

Bio:
Joe LeBritton has been the CAD Manager at Signal Processing Technologies since 1984, where his duties include managing IC layout, modeling and mixed signal simulation, IC layout verification, and system hardware/software. He received a PhD in Physics from the University of Rochester in 1979. He has held research faculty positions at the University of Rochester and the University of Arizona, and worked as a CAD Engineer at Burr-Brown Corporation.

Title: Modulo RNS Arithmetic Adder and Multiplier Implementation
Authors: Eid Al-Radadi and Pepe Siy
Org: Department of Electrical and Computer Engineering Wayne State University, Detroit, MI 48202
Email: ab1000@wayne.edu and psiy@ece.eng.wayne.edu
Phone: 313-577-8846

Abstract:
Residue Number System (RNS) is a non-weighted system, which results in a carry free arithmetic operation and supports high-speed concurrent computations. Specifically, addition, subtraction, and multiplication can be carried out on each residue digit concurrently and independently. RNS has demonstrated a high efficiency in implementing different types of digital filters. It has been successfully implemented in applications involving the design of fast number theoretic transform, discrete fourier transform, and many other areas. Therefore, designing an efficient modular multiplier and adder is important in realizing different high-speed RNS-based applications.

Most RNS adder and multiplier designs presented in literatures were based on modulo . However, many popular modulo set contain modulo other than . In this paper we extended the design of RNS adder and multiplier to modulo , where a=1 or a= , m

In this paper, we have given new procedures to design modulo adders, for both a=1 and a= . The implementation of modulo adder is using Carry Look Ahead (CLA) adder with simple correction. In the implementation of modulo adder, we use CLA adder with look-up table to do the correction.

Also in this paper, we present modulo multipliers, where a=1 or a= . The implementation of this modulo multiplier is based on using simple cells, which leads to efficient VLSI realization. The proposed adders and multipliers are faster than previous works. The implementations of the algorithms were written using VHDL codes behavioral models or structural architectures and simulated by using Mentor Graphics' Modelsim. The codes were synthesized using Exemplar's Leonardo Spectrum with the use of ADK (ASIC Design Kit) cells library, provided by Mentor Graphics Higher Education Program. The simulation of the circuit used Quicksim simulator, which incorporate time delays in the simulation.

Bio:
Eid Al-Radadi is a Ph.D. student at Wayne State University in Detroit, Michigan. His research interests in computer architecture and VLSI designs. He received his BSEE from University of Detroit Mercy and his MSEE from Wayne State University.

Pepe Siy is an associate professor in the Electrical and Computer Engineering department at Wayne State University. His research interests are in the areas of VLSI, Residue Number Systems architecture, and Image Processing. He received his BSEE from Mapua Institute of Technology, Philippines, his MSEE at University of California, Berkeley, and Ph.D. at the University of Akron.

Title: A Comparison of Two VHDL Memory Modeling Techniques
Author: Richard Munden
Org: Acuson
Email: munden@acuson.com
Phone: 650-694-5523 v
Fax: 650-943-7260 f

Time Required: 20 minutes

Abstract:
This paper will compare the Shellor method of modeling large memories with the new VITAL2000 method. The simulation of large memories is a common requirement for board design verification. The comparison will look for differences in capacity (computer memory required) and simulation speed of each method. The comparsisons will be done using ModelSim.

Bio:
Richard Munden has been using and managing CAE systems since 1987. He has been concerned with simulation and modeling issues for as long.

Richard co-founded the Free Model Foundry (http://vhdl.org/fmf/) in 1995 and is its president and CEO. When not teaching VHDL modeling classes for MT Associates, or VHDL classes for the University of California, Santa Cruz Extension, he has a day job as CAE manager at Acuson Corporation. Prior to joining Acuson, he was a CAE manager at TRW in Redondo Beach, CA. He is a well known contributor to several EDA users groups and industry conferences.

His primary focus over the years has been verification of board-level designs.

Title: Pick It, Click It, Get Information
Authors: Sarah Leritz-Higgins and Angelique Herran
Presenters: Sarah Leritz-Higgins and Angelique Herran
Organization: Mentor Graphics Knowledge Products Division
Email: sarah_leritz@mentor.com; angelique_herran@mentor.com
Phone: Ms. Leritz - (408) 487-7166; Ms. Herran - (720) 494-1106
Fax: Ms. Leritz - (408) 487-7001; Ms. Herran - (720) 494-0457

Time Required: 30 minutes

Abstract:
Paper showcases some upcoming Mentor products that will incorporate the new online-help system initiatives. Pick It, Click It, Get Information reviews a wide variety of new information technology methods (such as embedded help) along with other state-of-the-art technologies. Presenters will show how Knowledge Products Division works as a business partner with the other product divisions of Mentor Graphics to provide new, innovative ways to deliver technical information to the end user. Ms. Leritz will showcase the Embedded Systems Division product that will be ready /released by October 2001. Ms. Herran will showcase a Mentor Graphics application that is targeted to work with Mentor simulation products - first being the DesignView Analog-Mixed Signal simulator.

Mentor Products: TBA

Bios:
Both presenters are active members of the Society of Technical Communicators (STC) and technical speakers. Ms. Leritz presented at the 1999 WinWriter's Conference the paper, "Stomping Out Bugs!" and was selected to be a Peer Showcase presenter at the 2000 WinWriter's Conference. Ms. Herran has presented at previous VBUG conferences, International MUG 2000, 1996 Association for Computing Machinery (ACM) conference and STC regional conferences.

Sarah Leritz-Higgins has worked in the Silicon Valley software industry since 1996. Before becoming a technical writer in 1997, Sarah worked as a technical support engineer for five years. While assisting customers with software functionality and troubleshooting, she discovered the critical role of online help in the user experience. From the perspective of a support engineer, Sarah works to develop genuinely effective user-assistance.

Angelique Herran carries over 15 years experience in EDA design and tools and currently is a Knowledge Products Developer for DesignView and Signal Integrity tools. Originally a designer in the PCB industry, Ms. Herran also worked for Computervision Corporation in a variety of roles from Application Engineer, Manager Customer Support Division to Marketing Support Manager.

Title: Putting the (Mentor) User in Usability
Authors: Jeanne Christiansen / Cathy Yaspo
Presenters: Jeanne Christiansen / Cathy Yaspo
Organization: Mentor Graphics Knowledge Products Division
Email: Jeanne_Christiansen@mentor.com; Cathy_Yaspo@mentor.com
Phone: Ms. Christiansen - (408) 487-7205; Ms. Yaspo - (408) 451-5632
Fax: Both: (408) 487-7001

Time Required: 30 minutes (plus)

Abstract:
Paper discusses usability evaluations recently performed using Mentor Graphics' Systems Design Division and Embedded Software Division XRAY Debugger products. These evaluations are helping the Knowledge Products Division (KPD supports many of Mentor's product divisions) to develop the next generation of online-help systems and other online or hardcopy documentation. The evaluation techniques included:
- User Surveys
- User Profiling
- Task Analysis
- Design Walkthroughs
- Heuristic Evaluations
- Documentation Prototyping
- An In-House Usability Study

Paper focuses on the history of the online help task team of the Knowledge Products Division and how the Mentor Users were active participants in this activity. In concert with the theme of the conference "Working Together to Reach New Heights," the paper presentation will show some of the evaluations that were performed, hear about how the results have affected the documentation design and contents, and users will participate in a live usability study.

Mentor Products: Systems Design Divisions' Board Station, Embedded Software Divisions' XRAY Debugger

Bios:
Jeanne Christiansen is a Senior Technical Writer with Mentor Graphics and has more than ten years of customer documentation experience in the defense, embedded software, telecom, gaming, and semiconductor manufacturing industries. Jeanne spent 15 years working as a System Engineer at Lockheed Missiles and Space Co.(now Lockheed Martin) and Applied Signal Technology performing a wide variety of work from requirements analysis and definition to software development and hardware/software integration. Jeanne carries a degree in Electrical Engineering (Utah State University) with graduate work in usability, signal processing, and system engineering.

Within the Society for Technical Communications (STC), Jeanne is also the co-founder and manager of the STC Silicon Valley Usability Special Interest Group (SIG). She is also a member of the Usability Professionals Association, ACM Computer-Human Interaction SIG (SIG CHI) and its Bay Area Usability Group, Women in Technology International (WITI), and the Society for Women Engineers (SWE).

Cathy Yaspo carries a BA Journalism (Reporting & Editing) and a Certificate in Managing the Development of Technical Information from UCSC with advanced coursework in developing online help, usability testing, and user interface design. She joined Mentor Graphics 7 years ago and has worked mainly with the PCB product documentation team. She looks for opportunities in her daily work to help influence user interface design and promote usability testing of new functionality. Presently, both presenters are working on the next generation of online help for Mentor products.

Title: Electronic Model Attachment
Author: Eli Tuber
Org: Eastman Kodak Company
Email: eli.tuber@kodak.com
Phone: (716) 726-9466
Fax: (716) 726-67881

Time required: 30 min

Abstract:
With the large variety of Field Programmable Gate Arrays (FPGAs) devices now available in the market, LMS librarians find themselves trying to keep up with all the new simulation models available for attachment to each of these devices. New devices with 200-1000 pins make model attachment entry complex, time consuming, and error prone. New FPGAs, require that the LMS librarians generate multiple symbols each containing a subset of the device I/O, that users may instantiate on their schematics. These, in turn, must be attached to individual simulation schematics with symbols that have inconsistent naming conventions.

At Kodak, we have developed Ample Userware that allows librarians to automatically map an LMS symbol to a Smartmodel or VHDL symbol with minimal user intervention. The program uses property information provided with available symbols to create port and global connections between Master and Slave sheets under each symbol. The program also provides users with confidence that any future changes or updates to pin assignments can be entered automatically into the schematic with minimal impact to simulation. Model Attachment time has been reduced by 16X for FPGA's using the new program.

Mentor Products: LMS_LIBR, DA_LMS

Bio:
Four years as Applications Engineer supporting the design engineering community with Kodak using Mentor Graphics tool set as well as third party vendor tools used for design and simulation. Twelve years working in Test Engineering, in PWB manufacturing. Graduated in 1985 from University of Puerto Rico with BSEE. Schedule Restrictions: I would like to attend Userware and presentations on DA to Expedition mtgs.

Title: Automatic FPGA Mapping
Author: Eli Tuber
Org: Eastman Kodak Company
Email: eli.tuber@kodak.com
Phone: (716) 726-9466
Fax: (716) 726-7881

Time required: 30 min

Abstract:
In recent years the increasing complexity of devices has added more work for design engineers and technicians who do manual schematic entry. Modern devices with 200-1000 pins make schematic entry more complex, time consuming, and error prone. New Field Programmable Gate Arrays (FPGAs) require that the LMS librarians generate multiple symbols, each containing a subset of the device I/O, that users may instantiate on their schematics.

At Kodak, we have developed Ample Userware, which automatically enters design data from FPGA vendors' output files into a schematic with minimal user intervention. The program uses standard output files from Altera, Xilinx, and Actel to automatically draw buses, ports, and off-sheet connections for the device selected on the schematic sheet. The program also provides users with confidence that any future changes or updates to pin assignments can automatically be entered into the schematic with minimal impact to layout or simulation. Schematics entry times for FPGA's have been reduced by 10X using the new program.

Mentor Products: DA_LMS

Bio:
Four years as Applications Engineer supporting the design engineering community with Kodak using Mentor Graphics tool set, as well as third party vendor tools used for design and simulation. Twelve years working in Test Engineering, in PWB manufacturing. Graduated in 1985 from University of Puerto Rico with BSEE. Schedule Restrictions: I would like to attend Userware panels and presentations on DA to Expedition mtgs.

Title: An ASIC application of the RSA algorithm.
Author: Ali Ziya Alkar, Remziye Sonmez
Presenter: Dr Ali Ziya Alkar
Org: Hacettepe University Department of Electrical Engineering
Email: alkar@hacettepe.edu.tr
Phone: +90 5323510846
Fax: +90 312 2992125

Time Required: 20 mins

Abstract:
Security is becoming an increasingly important feature with the growth of electronic communication. The Rivest Shamir Adleman (RSA) is one of the most widely used public-key cryptography systems. The operation required is the computation of the modular multiplication over a positive integer. RSA method has a very slow ciphering rate if used in software. The use of a specific hardware is the only reasonable solution to obtain a good performance. To speed up the modular multiplication and squaring the Montgomery multiplication is used to constitute the core of modular exponentiation operation. Various software algorithms are investigated and the Coarsely Integrated Operand Scanning (CIOS) method is selected for our application. This method realizes both modular multiplication and reduction at the same time. Thus in hardware, area and speed improvements over other types of implementations are obtained. The squaring is performed in parallel with the multiplication in the Modular exponentiation. We can also impose a tighter constraint on the word size so that the final subtraction in the algorithm can be removed which decreases the gate number and increases the speed. This design uses a high radix 32 bit word size Montgomery multiplication so that the constraint on the word size is naturally satisfied. In order to further improve the efficiency of our design we incorporated the Chinese Remainder Theorem with the efficient pipelining techniques. The design is synthesized to the 0.5µm ASIC technology.

Mentor Products: Renoir, Modelsim and Leonardo Spectrum, IC Tools with the ADK libraries.

Dr Ali Ziya Alkar
Hacettepe University
Dept. of Electrical Engineering
Beytepe Ankara 06532
TURKEY

Email: alkar@hacettepe.edu.tr
Phone: +90 5323510846
Fax: +90 312 2992125
Web: http://vlsi.ee.hacettepe.edu.tr

Bio:
1997 --Department of Electrical and Electronics Engineering, Hacettepe University, Ankara, Turkey
Assistant Professor
§ Active teaching experience in:
Solid State Electronics
Microprocessor Programming and Computer Architecture I
Microprocessor Programming and Computer Architecture II
Introduction to Computer Programming - Pascal
CMOS VLSI Design
Consultant
1997 - TUBITAK Bilten (Information Technologies and Electronics Research Institute, Ankara, Turkey
1998 - 2000Turk Telekom, Ankara, Turkey System Administrator
§ System Adminstration for the largest national ISP.
§ Consultant for the TURNET ISP.
§ Seminars on Sendmail, Domain Name System and File Transfer Protocol.
1995 - 1997 Military Duty in the General Staff Headquarters, Ankara, Turkey
Lieutenant
· Computer Engineering
· Responsible for Computer Education of Military and Civil Personnel in the Center
1988 -- 1995 Department of Electrical and Electronics Engineering, Hacettepe University, Ankara, Turkey
Research Assistant
· Teaching experience in:
Undergraduate Level:
Measurements Lab.
Microprocessor Programming and Computer Architecture Lab.
Established today's Intel 8085 Microprocessor Lab. in the department
1994 -- 1995 University of Colorado at Boulder, Colorado, U.S.A.
Research Assistant
· Department of Electrical and Computer Engineering
· VLSI High Level Synthesis Research funded by Fujitsu Japan

Title: DXF and IDF Import and Export
Author: Jeff Johnson
Org: Sercel, Inc.
Email: Jeff.Johnson@sercelus.com
Phone: 281-647-7241
Fax: 281-579-7505

Time Required: 25 - 30 min

Abstract:
A discussion and demonstration of the usage of Import DXF, Import IDF, Export DXF, and Export IDF. Tips and tricks to effective use, settings and their implications, limitations, how the board origin affects results, layer mapping, documentation aspects, editing of the default drawing cell (DXFcell), and the mapping of 3D cells within ProE will be discussed.

Mentor Products: WG2000.X - Expedition

Bio:
Jeff Johnson is an IPC Certified Designer with 16 years experience in the printed circuit design field. He is currently employed with Sercel, Inc. - a leading player in both the land and marine seismic acquisition industry. He is a member of the Houston chapter of the IPC Designer's Council and serves on the local Board of Directors. He received his BS degree in Engineering in 1980 from Texas A&M University.

Title: Lcable Add Connector/Component by Ref Performance Problems in House Solutions and Customizations
Author: Marcelo F. Aragão
Org: EMBRAER - Empresa Brasileira de Aeoronautica S.A
Email: marcelo.aragao@embraer.com.br
Phone: 55 12 345 4655

Time Required: 15 minutes

Abstract:
One great feature in Lcable tool is the possibility to share connectors and components by many users simultaneously, without loose pin control, that is to say that we will not have two or more users with the same pin from the connector or component on their diagrams. That feature is called Add Connector/Component by Reference, so if the user uses the commands inside this feature to place and change components or connector on their diagrams, they will be guaranteeing the pins control. This paper has as objective to show performance problems solutions for Lcable C4 Add Connector/Component by Reference process and some customizations included within that process in order to supply EMBRAER requirements.

The main changes those will be reported here will affect the two main functions of that process, $add_conn_by_ref and $update_pins_used. Those changes include some logical fixes in the original code and some fixes on the lock sequence.

The customization include within the original process is in order to hold the pin signal reservation for the reserved pins. This customization includes some changes on $add_conn_by_ref function, what takes to some process changes, and creation of some new features to deal with this new capability.

Mentor Products: Lcable

Bio:
I have been working at EMBRAER as Advanced Resources Engineer, responsible for Mentorgraphics environment and tools for one year and half. We use a mixed environment Unix/NT with cabling tools, Lcable and Viewware.

Title: Calculating Component Area Requirements
Author: Michael P. Walsh
Org: Mentor Graphics Corporation
Email: mike_walsh@mentor.com
Phone: 919.484.2505
Fax: 919.484.2540

Time Required: 30 Minutes

Abstract:
This paper covers the concepts and methods used to calculate the area used by a group of components. The group may consist of some or all of the components in a design database. This functionality can be used early in the design process to help ensure that the chosen package technologies have a chance of being placed on a printed circuit board.

Mentor Products: Board Station (Layout in particular)

Bio:
Mike Walsh is an Applications Engineering Manager for Mentor Graphics based in Research Triangle Park, North Carolina. Mike joined Mentor Graphics in 1992 as an Applications Engineer and is the author of a number of widely used userware applications such as iplot and da_batch. Prior to working for Mentor Graphics, Mike was a hardware design engineer and Mentor customer at Star Technologies. Mike holds a BEE from Villanova University.

Schedule Restrictions: If accepted I will likely only be attending MUG on the day I would present my paper. I would prefer to present my paper the same day as the MUG party if at all possible as it would allow me to spend some time with a lot of customers as well.

Title: Project Priority Management with ModelSim and Platform's LSF LicenseMaximizer
Authors: Arend Dittmer and Bill McMillan (Arend Dittmer, presenter)
Org: Platform Computing Corporation
Email Address: adittmer@platform.com
Phone: 905-948-4247
Fax: 905-948-9975

Time Required: 30 Minutes

Abstract:
Always under fire from the twin forces of competitive pressure and rapid technological change, the semiconductor industry has recently been hit hard by unusually broad demand declines, worrisome high energy prices and consumer uncertainty. The changing market conditions mean that semiconductor organizations must confront the additional threat of reduced operating budgets, including lower expenditures for new computing resources.

One of the main challenges for effective resource management is the alignment of hardware and software resource allocation with project priorities. It is desirable that in a situation of low utilization of computational resources, all projects have equal access to these resources. In case of a resource shortage, jobs for high priority projects should be\ able to take over resources held by jobs with a lower priority. With falling hardware costs due to an increased commoditization and software expenses typically exceeding hardware expenses multiple times, software licenses are the most common resource bottlenecks in today's EDA organizations. The effective management of software licenses is of particular interest in the context of functional verification. Anecdotal EDA industry evidence suggests that about 70% of the total compute time spent in the logical phase of the design process is spent performing functional verification. Using ModelSim's "Checkpoint and Restore" capability and LSF's LicenseMaximizer, an optimized priority based resource allocation scheme based on the availability of ModelSim licenses can be realized.

Mentor Products: ModelSim

Bio:
Arend Dittmer is an Integration Architect in Platform Computing's Business Development group. Arend is working with independent software vendors in the EDA industry on finding new synergies between ISV's and Platform's products. Arend joined Platform Computing in 1998 as a technical consultant. In this role he was involved in numerous clustering projects in the EDA industry. Before joining Platform he worked in second line support for Hewlett-Packard's German response center, focussing on HP-UX and compiler support. Arend holds the German equivalent (Dipl.-Ing.) of an M.S. in electrical engineering from the university Erlangen-Nuremberg

Schedule Conflicts: None at this time.

Title: Designing an Interconnection Network Test Bed
Author: Rhonda Kay Gaede (presenter), Deborah A. Butler, Matthew Sweet
Org: The University of Alabama in Huntsville
Email: gaede@ece.uah.edu
Phone: 256.824.6573
Fax: 256.824.6803

Time Required: 20 minutes

Abstract:
As part of an ongoing research effort, an interconnection network test bed is being implemented at the University of Alabama in Huntsville (UAH). This implementation is aided by the use of Mentor's FPGA Advantage and Expedition tools. UAH is involved in a continuing project focused on investigating and developing optical interconnection networks. Consequently, a broadcast network exploiting the unique properties of optics has been proposed. Central to this network is receiver hardware which processes messages without involving the host processor. An electrical implementation facilitates the exploration of issues related to distributed computing. This test bed will also be used to investigate communication issues such as using reservations to assure quality of service, flow control, and implementation of collective operations such as broadcast and multicast. Programmable logic gives us the flexibility we need in this design. Xilinx XCV812E FPGAs on Xilinx AFX BG 560-100 development boards are used in this project. The test bed connects eight processors completely, that is, every processor can communicate with every other processor without any intermediate communication. The processors used are Motorola XPC 860 processors residing on PLX PCI 9054 RDK-860 boards and housed in host PCs. Development of the FPGA design is done using FPGA Advantage. The connections between the PLX boards and the Xilinx boards are accomplished through the design of piggy back boards for the PLX and Xilinx boards, a power distribution board, and a system distribution board. These board designs are done using Expedition.

Mentor Products: FPGA Advantage, Expedition

Bio:
Rhonda Kay Gaede received the BSEE degree from Southern Methodist University and the MSEE and PhD degrees from the University of Texas at Austin. She has worked for Motorola in Austin, Texas and IBM in East Fishkill, New York. She is currently an associate professor in the Electrical and Computer Engineering department at the University of Alabama in Huntsville. She is a member of IEEE, ACM, ASEE, AAUW, Tau Beta Pi, and Eta Kappa Nu. Her research interests include computer systems performance, optical interconnects, and computer architecture.

Schedule Restrictions: None Known

Title: Front End Board Design
Author: Panel from the Customer Support BA/LMS Team
Org: Mentor Graphics
Email: rick_reid@mentor.com
Phone: 503/685-7004

Time Required: 1.5 or 2 hours

Abstract:
Come and consult with our panel of experts who bring over 70 years of combined industry experience with Mentor Graphics tools. From part creation, library management, schematic capture through to layout meet with your Mentor Graphics Corporate Application Engineers to discuss the ins and outs of the tools that you use everyday.

- Learn how to leverage the front end design flow
- Discover tips for troubleshooting
- Learn the 10 most frequent calls to support and how to avoid them
- Compare Board Architect vs. to_layout
- Track the future of the board flow with SDS and DMS

Mentor Products: Library Management System (LMS), Data Management System (DMS), Design Architect, Board Architect, Layout, to_layout, Package, Librarian

Bios:
Amy Fisher: Amy Fisher has been with Mentor Graphics Support for 13 years. She supported Core BoardStation products for approximately 10 years, specializing in Hybrid Station, PTM:Site, and Manufacturing outputs. For the past 3 years, she has focused on the PCB processes and front-end packaging tools, BoardArchitect, Package, & SRP. Prior to Mentor, Amy worked as a Manufacturing Engineer for Lockheed, and as an engineering technician and board designer for EGG Reticon.

Wayne Lem: Wayne has been with Mentor Graphics 15 years and has distinguished himself as a leading expert in Mentor Graphics PCB tools. He currently supports the PCB board process tools.

Annette Grassi has worked for Mentor Graphics for 11 years focusing on PCB processes and front-end packaging tools. She currently supports the Board Architect and PCB board process tools.

Matt Killinger: Matt has been with Mentor Graphics Customer Support for nearly five years working initially with the Falcon Framework, then Design Architect, and most recently with the Board Architect support team. Matt has mapped his training in computer science and his 10 years of experience with the U.S. Marines into a go getter within Customer Support and an emerging authority in the realm of Mentor's schematic capture tools.

Bruce McAlary: Bruce has been with Mentor Graphics Support for 10+ years. He supported Design Architect & DVE for 6 years, for the past 4 years he has been supporting the Library Management System's set of tools including da_lms, lms_libr, PDS, the BPL Library, symbol genie & AXEL. In a consulting role with Mentor Graphics, for 1 year, he created & implemented a corporate wide Process Integration test program including Application Installation Test to validate the installability of all MGC products prior to release to manufacturing.

Prior to Mentor Graphics, Bruce worked at Tektronics for 10 1/2 years as a QA engineer on Design to Test Integration Tools & Logic Analyzers, as a Physical Layout Product Specialist for automated design capture thru manufacturing tools focused on the PCB design process, Factory Applications Engineer & CAD schematic capture, all centered around CAE/EDA tools.

Al Messersmith: Al has been with Mentor 4 1/2 years focusing on DA and LMS products. He currently supports the Library Management suite of tools (LMS). Prior to joining Mentor, Al spent 10 years with Hewlett Packard as a board designer and as a technical support engineer for HP EDA tools (schematic capture and board layout).

Bio:
Rick Reid has worked for Mentor Graphics for 13 years focusing on data management, part management and application customizations. Prior to joining support, Rick worked as a technical writer for Falcon Products and did his "time" in technical marketing for process and design data management. He currently supports the Library Management suite of tools (LMS).

Title: Process and Tools Training: Establishing a Broad Base
Author: Tony Defina
Organization: Northrop Grumman ESSS, Baltimore, MD
Email: anthony_f_defina@mail.northgrum.com
Daytime Phone: 410-993-3273

Length: 30-45 minutes

Abstract:
A few years ago, Northrop Grumman instituted Mentor Graphics as its core EDA tool of choice. The first Mentor users at Northrop Grumman were digital design engineers and PWB draftsmen. More recently, Northrop has been expanding its Mentor use to MCM, RF and antenna manifold technologies. Faced with a large set of users that had no Mentor experience (and most of whom have never dealt with schematic-driven design), Northrop found the initial going to be rather rough, particularly when the technology and the tools were being stretched.

It was soon determined that the core problem was one of education and vocabulary. Therefore, Northrop embarked on putting together a training curriculum that would be timely, accurate and maintainable.

Key to the Northrop training deployment for ECAD training is the idea that everyone involved in the design and realization of electronic design, from management to technicians, needs to be able to speak intelligently to the ECAD design process and the tools that are being used in the process.

The result is a complete training curriculum that contains several modularized courses that can be adjusted for differing audiences but contain the same core information. The classes in the curriculum are based upon the Northrop ECAD process and are steeped heavily in the tools.

Northrop Grumman has begun to deliver the courses in the First Quarter of this year and is planning innovative delivery in the near future.

Mentor Products: Design Architect, Board Station, QuickSim, AccuSim, ICX, and more.

Biography:
Tony Defina is an ECAD Engineer with the Northrop Grumman Process and Tools Development Support (PTDS) department. PTDS supports a variety of CAD design tools throughout Northrop Grumman's Electronics Systems Sensors Sector.

Tony has worked with Northrop Grumman for over three years. He has been a Mentor user since 1983 and is a member of the MUG Steering Committee.

Title: A Few ExAmple Concepts
Author: Alfred W. Wainwright, Jr.
Org: Lockheed Martin NE&SS-Surface Systems
Email: Alfred.W.Wainwright@lmco.com
Phone: 856/722-4320
Fax: 856/722-4410

Time Required: 30 min.

Abstract:
Ample users have been practicing their craft for almost ten years now, and have explored and honed programming techniques in this language far beyond the original vision of the Falcon Framework authors. And, regardless of whatever evolutionary track Ample takes in the future, there have been valuable lessons learned, and powerful concepts realized. Hopefully, such information can be filtered back into the next level of language development, resulting in even greater advances in functionality, usability, reliability, performance, and supportability. This presentation will detail a few of the author's favorite uses of Ample to accomplish common tasks, by way of exAmple (extracted Ample). These code snippets are intended to provide the audience with some fresh ideas that may be applicable in their own Ample development efforts to improve speed, acquire data, simplify processes, enhance documentation, and research solutions. Many of the concepts to be discussed would be useful and desirable features in any application program interface.

Mentor Products: Ample, Common User Interface

Bio:
Al Wainwright attended Drexel University, and became involved with computer aided design in 1974 using Applicon Graphics Systems. He joined RCA in 1979, and was subsequently employed by GE Aerospace, Martin Marietta, and Lockheed Martin, through acquisition and merger. He also worked for L3-Communications briefly in 1997. In 1982, he became a Mentor user, and in 1988, he started using Boardstation. He is currently a senior member of the engineering staff at Lockheed Martin in Moorestown, NJ, performing design automation activities.

Schedule Restrictions: Attending 10/1-10/3

Title: Putting FlexLM reportlogs to work for you.
Author: Rachel Stanley
Org: Honeywell Inc.
Email: rachel.stanley@honeywell.com
Phone: (727) 539-2566
Fax: (727) 539-3537

Time required: 20 minutes

Abstract:
FlexLM has the ability to generate encrypted log files that accurately reflect actual license usage. Now with the assistance of Globetrotter Inc.'s SAMSuite, specifically the SAMReport component, you can create graphs and reports for a wide variety of uses. This paper and presentation will share best practices to how we have successfully used the web-viewable, importable, and printable SAMSuite reports to better manage our location and continentally floated licenses.

Mentor Products: Licensing of all products.

Bio:
Graduate of Eckerd College with a Bachelor's of Science degree in Computer Science. A former intern with the United States Geological Survey. Currently working as a system administrator with Honeywell Space Systems in Clearwater Florida.

Schedule Restrictions: None.

Title: An Implementation of Concurrent Engineering
Author: Olivier Danoy
Org: Advanced Micro Devices
Email: olivier.danoy@amd.com
Phone: (512) 602 7813
Fax: (512) 602 7807

Time Required: 20 mins

Abstract:
This presentation will discuss an implementation of the Concurrent Board Process using Design Architect and Board Architect. It will show the design process used to enable Concurrent Engineering, such as creating viewpoints and promoting designs, using a combination of custom userware and PCBGen. The paper will also highlight some of the issues and solutions associated with the implementation of the Concurrent Board Process.

Mentor Products: Design Architect LMS, Board Architect LMS

Bio:
Olivier Danoy is a Member of Technical Staff in CAD Systems Engineering located at AMD's Austin, Texas facility. He supports the EDA software used by the platform engineering organization, develops and documents custom userware to automate the design process including the Concurrent Board Process. He has been using Mentor Graphics tools since 1986 in Australia and the United States. He holds a Master degree in Electrical Engineering from the "Ecole Nationale Superieure des Telecommunications de Bretagne".

Title: Zero to Boards in 6.8 Weeks
Author: Greg Dance (Presented by Greg Dance and Robert Marin)
Org: AirPrime
Email: Greg.Dance@airprime.com Robert.Marin@airprime.com
Phone: 760-476-8676 760-476-8686
Fax: 760-476-8701

Abstract:
Join Greg Dance and Robert Marin for an insightful look at what it takes to start off with nothing and rapidly put the infrastructure in place to design high technology products in the shortest amount of time. Greg and Robert will be discussing how in less than 7 weeks (including Christmas break), their team went from bare laptops with no tools installed to the board fabrication of a wireless device that worked on the first revision. They will show process flows and tools that helped them become productive as fast as possible. They will also discuss how they utilized the ASCII capabilities of the Library Manager to bulk upload complete libraries.

If you are just looking at switching over to the Expedition toolset from the Boardstation ones, this is the session to catch.

Bio:
Greg Dance is Sr. Manager of PCB Design for AirPrime, Inc. an OEM of CDMA wireless products. Greg has worked with Mentor BoardStation products as a designer, system administrator, manager and consultant. Tasked with starting up a PCB group for a start-up wireless company he chose the Design Capture/Expedition family of products as the foundation for their new designs.

With over 20 years experience in the PCB design arena Robert Marin has worked in applications ranging from High-Rel Military designs to high density consumer products mass produced in the millions. The last 6 years have been in high density handset applications using the latest HDI technologies. Robert has joined various start-ups during this time and is experienced at setting up a PCB group from the ground up, including such tasks as EDA Tool bench-marking, selection and integration.

Title: Finding a Needle in the Haystack - Design-Wide Searches in Design Architect
Author: Andrew W. Green
Org: QCP Inc. representing Kyocera Wireless Corporation
Email: agreen@qcpi.com
Phone: (858) 882-2193

Abstract:
A recurring complaint amongst Mentor users is that it is very difficult to find specific data in a schematic design. To locate a particular component, net or any other object requires that the user opens DVE on a viewpoint and uses this tool to locate the desired data. It would be much more convenient if the user could simply locate the required data within Design Architect.

This paper presents a programmatic solution to this problem: a search engine that utilizes the powerful Design File Interface functionality that is available from within Design Architect. This allows the user to quickly locate property/value pairs anywhere in a schematic design, even through multiple levels of hierarchy.

Matches are presented to the user in an intelligent report; any match can be selected and opened with a single mouse click.

Bio:
Andy Green has been a CAD designer for over 20 years. Now Senior Staff Applications Engineer at QCP Inc. representing Kyocera Wireless Corporation (KWC) in San Diego, CA, his role is focussed on design automation and process development, writing and customizing CAE tools to integrate them into the KWC environment.

Title: Using WorkXpert for problem solving and library data control
Author: Bruce Mayer, Northrop Grumman - Litton Advanced Systems
Email: Bruce_Mayer@LittonAS.com
Phone: 301-454-9154
Fax: 301-454-9747
Time Required: 30 min.

Abstract:
Here is the problem we needed to address, "How can Thermal Engineers minimize redundant calculations and input resultant data into the catalog files and geometries a) without teaching them lms_libr and librarian, b) without compromising the integrity of the catalog and library geometry data and c) provide accountability and repeatability to the data provided?". The answer is to take advantage of the WorkXpert interface. WorkXpert provided an intelligent GUI that is easy to learn and use. The new thermal data flow has also become an extension of the existing PDS flow tools used within Litton Advanced systems to develop libraries. This paper will look at the user aspects of this flow and provide an overview of techniques used within the flow.

Bio:
Bruce has worked in the Electronic CAD/CAM industry for over 18 years. His CAD experience includes ComputerVision's CADDS 1, 3, 4/4X, Zuken's Theda and Mentor's BoardStation. During the last 12 years, his primary focus has been to develop tools which improve design quality and Engineer/Designer efficiency.

Title: A comparison of IS simulations vs. measured lab results in the Common Hub Modules designed at the Mobile Satellite Systems Division of Hughes Network Systems.
Authors/Org: Shahana Tanveer (Hughes Networking Systems), Mitra Geeban (Mentor Consulting)
Email: stanveer@hns.com; mitra_geeban@mentor.com
Phone: Shahana Tanveer - 240-453-2172; Mitra Geeban - 301-721-7616
Fax: Shahana Tanveer - 240-453-2201; Mitra Geeban - 301-990-1269

Abstract:
Up front signal integrity analysis at the module level is becoming more and more critical due to the increasing operating frequencies of digital circuits, faster edge rates etc. In today's fastest time to market business model, development schedules call for a first pass success on module PWB designs. At Hughes Network Systems (HNS) the challenge for the Mobile Satellite Systems division was to design the Common Hub modules with first past success. This meant eliminating any potential problems due to Signal Integrity issues. The Common Hub project was the first project that HNS to use Mentor's IS tools for board level signal integrity analysis, and was carried out by HNS engineers working with Mentor Consulting. This paper documents the methodology used, and offers a comparison of IS simulation versus lab measured results.

Bio
Shahana Tanveer has been a hardware engineer for the Mobile Satellite Systems division of Hughes Network Systems, Germantown, Maryland for the past 3 years. Shahana has a B.S.E.E. from the University of Maryland, College Park.

Mitra Geeban has been a consultant for Mentor Graphics for over 4 years, prior to that he worked as an engineer at Motorola LMPS. Mitra has a B.S.E.E. from the University of Miami.

Title: Wire Harness Design and Manufacturing
Author: John S. Low
Organization: Mentor Graphics Harness Systems Division
Email: john_low@mentor.com
Phone: 425-452-1595

425-451-4762

Abstract:
This session consists of a presentation and demonstration. The presentation will describe the newest release of the Logical Cable product line. Additionally, the presentation will explain how the Capital Harness Systems products broaden Mentor Graphics' solutions for wire harness design, analysis and manufacturing. A short demonstration showing the Logical Cable to Capital Manufacture process flow will follow the presentation.

Bio:
John Low is a Product Manager for the Harness Systems division at Mentor Graphics. He has ten years experience in the definition and support of wire harness applications at Mentor Graphics. In addition, John has experience supporting the CATIA wire harness applications and has done aerospace process and software tools consulting in such companies as Boeing, Raytheon Aircraft and Bombardier.

Title: Interfacing Expedition PCB to Capital Harness Software
Author: Tony Gilbert
Org: Micromass UK ltd.
Email: tony.gilbert@micromass.co.uk
Phone: +44 161 718 4545
Fax: +44 161 998 8915

Abstract:
Many electronics systems consist of one or more printed circuit boards (PCBs) connected to each other and the outside world with a wiring harness. Expedition PCB is a tool for printed circuit board design, and Capital H is a tool for defining wiring harnesses. This paper describes a method for using data extracted from PCB designs to automatically populate wiring harness database with connector and wire data. The methodology used is to identify all connectors and their associated nets on PCBs, and to translate these to mating connectors and wire lists in the harness. The result being a faster and more accurate definition of the wiring harness than would otherwise be achieved. The benefits of this approach are reduced rework of the design at the system level, and ultimately faster time to market.

Bio:
Graduate in Electrical Engineering from Imperial College, University of London 1971. Previously held various design related positions in the electronics industry. Current position Product Manager at Micromass UK ltd. Responsible for specification and design of analytical instruments (mass spectrometers). Multi-disciplinary responsibilities include electronics, ion optics, vacuum technology, chemistry. Outside interests include mountaineering, literature and music.

Title: Managing Design Automation Licensing Using SAMsuite and the Web
Authors: Nick DeMatt and Phil Lindberg
Org: Applied Physics Laboratory and Northrop Grumman Litton
Email: Nick.DeMatt@jhuapl.edu, Phil_Lindberg@littonas.com
Phone: 301-454-9587, 240-228-9082

Abstract:
Are you responsible for managing the licensing for your Mentor Graphics tools? If so, you've likely experienced that sinking feeling associated with trying to understand the licenses you own, how they're being used, and if you're making best use of your investment in the tools.

We'll review our use of the Globetrotter tool SAMsuite, particularly as it relates to managing design automation tools like Mentor Graphics. SAMsuite is a centralized license management and report tool, brought to you by the same folks who make FlexLM, Globetrotter. It offers the ability to manage your application license from a single interface, and create reports to help you understand license usage.

Creating report logs on heavily used tools with complicating factors like redundant servers can be a headache. Here's your opportunity to learn from our experiences using SAMsuite in real world environments.

This presentation will also cover our recent attempts to make results from SAMsuite reports available automatically through the web. You'll want to learn about this if you've ever been cornered by a manager who wants to know where all of this money is going, and you didn't have a way to display it immediately. We'll show you how to automatically create license usage reports even your manager can understand, and distribute them through your intranet.

Bio:
Nick Dematt is a member of the Technical Services Department at the Applied Physics Laboratory. He is responsible for managing a CAE facility that provides everything from hardware to software support. He holds a Bachelor of Science degree in Electrical Engineer and has nearly 15 years of experience using design automation software.

Philip Lindberg is a member of the Engineering Design Services group at Northrop Grumman Litton Advanced Systems. He is responsible for the electrical design environment, including Mentor Graphics user support, training, andenvironment customization. He holds a Bachelor of Science degree in Electrical Engineering. The Engineering Design Services Groupsupports Advanced Systems' military, space, and telecommunications design and manufacturing efforts.

Title: Animation of a VHDL Model in Modelsim Using Tcl/Tk
Authors: Dave Sullins and Hardy Pottinger
Org: Univ. of Missouri-Rolla
Email: hjp@ee.umr.edu

Abstract:
Visualization of the operation of a processor model is a difficult process that can be made more attractive by using Tcl/Tk procedures built into Modelsim. This paper describes the use of Modelsim and Tcl/Tk to display and animate a block diagram of a synthesizable model of a subset of the 8051 microcontroller (WIMP51). The model is being used to introduce Electrical and Computer Engineering undergraduates at the University of Missouri - Rolla to computer architecture and the 8051. The WIMP51 is binary compatible with a subset of the 8051's instructions, can be programmed with a standard 8051 assembler, and can be realized in a Xilinx 4005 FPGA.

Bio:
David Sullins teaches an undergraduate laboratory course in hardware software co-design. He received his BS in Computer Engineering from the University of Missouri-Rolla in 2000, and is currently working on his MS in Computer Engineering there. He is interested in VLSI design and hardware software co-design. Hardy Pottinger is Director of the Computer Engineering Program at the University of Missouri - Rolla. He is a past president of MUG and currently serves on the steering committee.

Title: A New Technique for Modeling Special Power MOSFET
Author: Wael El Manhawy, Wael Fikry
Org: Mentor Graphics
Email: wael_manhawy@mentor.com

Abstract:
This papers presents a new method of marcomodeling of special power MOSFETs that contains irregular I D - V GS characteristics. The new macromodel achieves this irregular behavior plus having accurate capacitance measurements and no convergence problems.

Bio:
Wael El Manhawy is an employee in Mentor Graphics Egypt. He works as a development engineer in the AccuParts team, and with a focus in macro and behavioral modeling.

Title: Fixing the "Split" Symbol Problem and Other Nifty QuickSim/QuickSim Pro Enhancements
Author: Paul Ree, Samy Nada
Org: Mentor Graphics
Email: paul_ree@mentor.com; samy_nada@mentor.com
Phone: (503)685-0146
Fax: (503)685-1915

Abstract:
One of the most irritating problems which has plagued users for a number of years is the situation involving a symbol that is so large that it has to be broken up into two or more subsymbols. This presents a huge challenge for those users that want to simulate since you cannot break up the simulation models. Up to this time, users have had to live with a workaround developed and published by yours truly over seven years ago. This workaround, however, is extremely cumbersome. The friendly, smiling folks responsible for QuickSim and QuickSim Pro take great pleasure in announcing that we have now addressed this problem and will provide a simple, easy way for our users to set up and simulate split/fractured/non-homogeneous symbols. In addition to this overdue enhancement, other important enhancements are being made to the tool set of which you should be aware. This session will not only give you the technical details on our split symbol fix, but also give you a roadmap of the enhancements we plan on making to QuickSim and QuickSim Pro.

Bio:
Paul Ree is the Technical Marketing Engineer for QuickSim products. Previously, Paul worked as the Technical Marketing Engineer for QuickSim in 1999, before moving onto a Technical Marketing position for FPGA Advantage. Paul has extensive experience as a Support Engineer for LMS, QuickSim and IDEA station products. Before joining Mentor in 1990, he worked for a variety of electronics firms, including Kaiser Electronics, Hughes Aircraft and Northop Corporation. Paul Ree has a BSEE from the University of California, Irvine.

Samy Nada is a Software Development Engineer for QuickSim Products. After graduating from Ain Shams University, Cairo, in 2000, he has been employed by Mentor Graphics as a development engineer for QuickSim, QuickFault, and QuickGrade.

Title: BGA Design Using Expedition
Authors: Jeff Johnson and Shaun Olson (team presentation)
Org: Sercel, Inc. ; Intel
Email: Jeff.Johnson@sercelus.com and Shaun.m.olsen@intel.com
Phone: 281-647-7241
FAX: 281-579-7505

Abstract:
A discussion/demonstration of the issues involved with implementing BGA's in the Expedition design environment.

Keys to effective usage include:

1. Library cell topics (fan-out within cells(pros n. cons), built-in fiducials, markings and registration).
2. Padstacks (via-in-pad, micro-vias, blind vias, SolderMaskDefined pads, non-SolderMaskDefined pads).
3. DRC conditions (DRC by area, rules by area).
4. Fan-out strategies (pre-placement of vias, line widths by area, additive layers).

Demonstration of fan-outs and routing of a BGA design will be included.

Bio:
Jeff Johnson is an IPC Certified Designer with 16 years experience in the printed circuit design field. He is currently employed with Sercel,Inc. -- a leading player in both the land and marine seismic acquisition industry. He is a member of the Houston chapter of the IPC Designer's Council and serves on the local Board of Directors. He received his BS degree in Engineering in 1980 from Texas A&M University.

Shaun Olsen has been designing PCB's for almost 7 years (6 years using Veribest) and is currently a Senior Designer with Intel Corporation (in a group that develops and/or provides processor/chipset and system debug tools that are used by both internal Intel validation labs as well as external OEM customers who are developing early systems using new iA32 or iA64 components). He received his BS in Anthropology from the University of Utah in 1996 and is currently pursuing an MBA in e-Business with the University of Phoenix.

Title: But What About the Little Ones?
Author: Michael J. Haney
Org: High Energy Physics, University of Illinois
Email: m-haney@uiuc.edu
Phone: 217-244-6425
Fax: 217-333-4990

Time required: 30 mins

Abstract:
While the rest of the world may be moving on to FPGAs and CPLDs, there are legacy designs in service that employ older, smaller PALS, PLDs, and similar small-silicon programmable devices. What tools are out there? Are the free tools worth their price? What are the options, when antiquity refuses to pass into history. I am not sure there is an appropriate Mentor product, anymore... (FPGA)

Bio:
Michael J. Haney is a Research Engineer with the High Energy Physics Group of the University of Illinois. His group designs high speed digital and analog control and data acquisition electronics for particle experiments at national laboratories. He is currently engaged in the design of the Muon Trigger for BTeV at FermiLab, and instrumentation for testing the LH2 absorber window for MuCool. Michael received his Ph.D. in Electrical Engineering in 1985 from the University of Illinois, is a member of the IEEE and ACM, and has served (in one capacity or another) as a VBUG officer since 1997.

Schedule conflicts: None

Title: WG2000.05, Out of the Box
Author: Dwain Strang

Time required: 60 mins

Abstract:
You have just opened your new CD of Mentor Graphics software and now you need to know what to do and how to setup your new EDA CAD system… Offered from a users perspective, this presentation includes: what to install from the WG2000 CD; some concepts in setting up libraries; what are those .asc files; there is a Windows printer setup file; DXF import, export, and those pesky CAD working units; CAD seed files and WG2000 templates; how often do you need to backup - libraries and jobs; nested cells and misc hardware - quick BOM stuff.

Mentor Products: Expedition DesignCapture, DesignView, and PCB

Schedule conflicts: None

Title: ASIC Library Verification
Author: Amira Omar and Doaa Nassar
Speaker: Doaa Nassar
Mentor Graphics Egypt
Email: doaa_nassar@mentor.com
Phone: +20(2) 414 1306
Fax: +20(2) 418 6945

Time required: 20 min

Abstract:
To ensure the correctness of the ASIC libraries used in LeonardoSpectrum, library verification tool has been developed. As the manual verification process consumes a lot of time and effort, the need of such tool becomes an urgent customer necessity.

In this article, we present a fully automated tool using the state-of-art technology including FormalPro and ModelSim for both functional and timing verification. A Tcl based interface is developed to fully integrate the developed tool inside LeonardoSpectrum.

The objective is to assist the user to verify the content of the ASIC library. The tool performs some general library properties verification demonstrating the contents of the library as wire load tables, timing information for each cell and operating conditions. In addition it perform functional verification using either ModelSim or FormalPro.

In case of ModelSim it writes the netlist of the library cells as VHDL files for the same cell before and after mapping to the specified library, automatically creates a test bench for each cell from the obtained VHDL files to be simulated using ModelSim to compare the outputs. And in order to assist library developer to verify accuracy of delay calculation on LeonardoSpectrum, we have implemented a timing verification process, that takes the library and processes the cap_load_range and num_samples on the required cell to be verified, then write SDF files as an output netlist or either all the cells in the library or for a specified cell. Library developer can then verify the output timing data.

For LeonardoSpectrum Modgen verification (module generator like half adders, full adders, half subtractors, full subtractors, etc.), the tool reads in a set of basic operator design and running optimization, then reports the cell usage in the design. Finally we verify the DRC (design rule checking) on a specified design work satisfactory for the specified library.

Bio:
Doaa Nassar is a development engineer working at EXEMPLAR, "LeonardoSpectrum ASIC libraries." Doaa has been graduated from Cairo University in 1997 from Electronics and Communication Department. Before joining Mentor Graphics, Doaa worked as a digital designer in IEP, Cairo Egypt.

Title: Classic Library to Expedition Library Conversion
Author: Joel Blend
Org: Sandia National Laboratories

This paper will discuss the issues and goals for converting from the Mentor classic environment to the Expedition environment. The paper will outline the customer's goals in adding Expedition to their design flow, how the transition was made with the help of Mentor Consulting, and what benefits they have accrued.

With customers that have been using the Mentor classic tool sets for many years, the gating factor to new tool introduction is the library data. There are countless hours and dollars spent on creating and verifying the integrity of the data in a corporate library. There are legacy design issues and migration of tools issues that have to be considered.

The conversion of the library data can be done in two distinctly different ways. One way is to convert all the library data and start creating designs in the new environment. The second way is to do an incremental conversion having both tool suites running while verifying the integrity of the data. Sandia is using the incremental conversion using a nightly or "on command" conversion capability to keep the LMS and Expedition libraries synchronized. Installing this conversion process data required some manual configuration and clean-up to ensure the Expedition library is configured to take advantage of new features and capabilities introduced with a new suite of tools.

Title: On Displaying the Interface of a Remotely-Run Tool on Linux
Author: Georges Antoun and Hazem Abbas
Org: Mentor Graphics - Egypt
Email: georges_antoun@mentor.com and hazem_abbas}@mentor.com

Time required: 20 mins

Abstract:
This paper addresses the problem of running a Mentor tool (ICGen) remotely and displaying the interface on a Linux box. The problem is mainly due to the failure of the tool to allocate colors for linux. The importance of the approach used here is that it can be extended to other Mentor tools that run perfectly on Solaris but pose troubles when displayed on Linux boxes. The approach adapted in this paper is to handle the color allocation and storage for X-window systems using a different colormap structure than that usually assumed and used by the tool. The efficacy of this method will be demonstrated in the results.

Bio: Georges Antoun, born in Cairo - Egypt at July 26th 1976. He completed primary and secondary education at Jesuites school and graduated from Cairo University, faculty of engineering 1999, department of Electronics and Electrical Communications. General appreciation: distinction with degree of honor, rank 6th. George has worked in Mentor Graphics Egypt since 1999 until now as a development engineer. He has worked in development of many layout, compaction, placement and routing tools such as ICGen, ICStation and finally UPR.

Title: Vision for Linux in EDA

Time required: 60 mins

Abstract:
Attend this special session and hear from Sun, HP and Mentor Graphics about their plans around Linux.

Sun, HP and Mentor Graphics will share their vision for the future of the EDA desktop.

• Perspectives on whether Linux can compete and in which application
• Linux market growth compared to the UNIX operating systems
• EDA application development on Linux
• Interoperability between Linux, Windows, other UNIX

The panel moderator will direct questions to the participants during the first 40 minutes of the session. The remaining time will be devoted to questions from the audience.

Title: Cooking Show - Getting Started with FPGAS
Author: Michael J. Haney
Org: High Energy Physics, University of Illinois
Email: m-haney@uiuc.edu
Phone: 217-244-6425
Fax: 217-333-4990

Abstract:
In this first Episode we will cover setting up a project, and begin the design process. Flow charts and State diagrams. Digital Simulation, Synthesis & VHDL. Design Capture: Flat & Hierarchical.

Bio: See paper 40.

Title: Cooking Show - Design Capture/Libraries
Author: Michael J. Haney
Org: High Energy Physics, University of Illinois
Email: m-haney@uiuc.edu
Phone: 217-244-6425
Fax: 217-333-4990

Abstract:
In Episode 2, we continue/finish Design Capture, and cover Library setup. Symbol editing, PDB editing, Cell editing, Hyperlinks. Finally, we enter the PCB editor.

Bio: See paper 40.

Title: Cooking Show - PCB
Author: Michael J. Haney
Org: High Energy Physics, University of Illinois
Email: m-haney@uiuc.edu
Phone: 217-244-6425
Fax: 217-333-4990

Abstract:
The focus of Episode 3 is PCB Place and Route, Rules by Area, Plane Layout, and DRC.

Bio: See paper 40.

Title: Cooking Show - End Game
Author: Michael J. Haney
Org: High Energy Physics, University of Illinois
Email: m-haney@uiuc.edu
Phone: 217-244-6425
Fax: 217-333-4990

Abstract:
Finally, in Episode 4, we cover silkscreens and drill maps, Thermal & Gerber (Photoplotter) CAM output, and end with the Cooking Show Rap-up and Questions.

Bio: See paper 40.

Title: O/S Forum
Authors: Nick DeMatt and Scott Cate
Org: Applied Physics Laboratory and Mentor Graphics
Email: nick.dematt@jhuapl.edu, scott_cate@mentor.com
Phone: 443-778-8092, 503-685-4849

Abstract:
This session is targeted to those using, supporting, or administrating Mentor Graphics tools, on undocumented hardware and operating system platforms. You will hear the experience of one user and helpful information Mentor Graphics.

For the past year, APL has been operating our CAE network on HP-UX 11.00. With only a few minor modifications, we have successfully deployed over 15 different EDA vendor software applications to our customers. In addition, we are currently in the process of upgrading to 11i and testing the MGC Falcon tools. A matrix will be provided highlighting which versions of the different vendor applications are operating under 11.00 and 11i. A profile of workstation configurations will also be provided. This information is intended to help others with making decisions concerning future platform choices.

Mentor Graphics will discuss what the user community can expect from Mentor for support of platforms that appear after a software release. Topics will include - platform clones, "Alternative Platforms", and the risks and responsibilities of both Mentor Graphics and Mentor Graphics users on undocumented platforms.

Bios:
Nick Dematt is a member of the Technical Services Department at the Applied Physics Laboratory. He is responsible for managing a CAE facility that provides everything from hardware to software support. He holds a Bachelor of Science degree in Electrical Engineer and has nearly 15 years of experience using design automation software.

Scott Cate has been part of the Mentor Graphics Customer Support Division for the past eight years. His expertise focuses on installation, licensing, and other environment/deployment issues.

Title: Powerful, Intuitive Synthesis for FPGA Design
Author: Tom Hill
Org: Mentor Graphics
Contact: tom_hill@mentor.com

The next generation multi-million gate FPSoCs (Field Programmable Systems-on-Chip) enable new capabilities to rapidly develop, prototype, and deploy entire systems that were once achievable only through advanced ASIC technology. These new devices require highly accurate and intuitive design tools that can readily integrate and synthesize microprocessors, IP cores, memory, and logic into these new devices. This session will introduce the Mentor Graphics synthesis environment, and let you experience the speed at which you can accomplish your next design challenge.

Title: Using Variants in PCB Designs (Variants are NOT Design Re-Use!!)
Author: Chuck Vroman
Org: Honeywell, Intl.
Contact: chuck.vroman@honeywell.com

Abstract:
The use of variants in PCB designs is relatively new to the Mentor tools suite. This presentation describes how variants are defined by Mentor and how they are used by Honeywell in the design of complex PCBs. The process for new designs is described first, followed by the different steps needed for design changes once the design database has been archived. The detailed variant processes are described with examples of output files and drawings. The discussion also describes why variants are not the same as design re-use.

Mentor Products: Board Architect, Design Architect, Layout, Fablink

Bio:
Chuck Vroman has worked for Honeywell Guidance and Navigation Operation in Clearwater, Florida for 18 years. He performs the role of CAD Support Engineer for PWB projects, processes and technology. Other assignments have included: design automation software development, Unix System Administrator, applications support for Mentor Graphics, Actel, and Xilinx tools, and Mentor librarian. Chuck has a Bachelor's of Science degree in Electrical Engineering from Florida Atlantic University.

Title: Developing Applications in Power Electronics: Automotive Systems
Author: Prof. Lauro de Vilhena Brandão Machado Neto
Org: PUC Minas - Brazil
Contact: LVILHENA@PUCMINAS.BR

Abstract:
This paper presents some applications of Power Electronics in Automotive Systems. It is a further step in the activities carried out by the group of the Power Electronics Laboratory - LABEP of the Polytechnic Institute of Pontifícia Universidade Católica de Minas Gerais - PUC Minas, Brazil, in collaboration with the Research Center of FIAT, in Turin, Italy, as part of the agreement FIAT - PUC Minas, Cooperation for Development.

The first application is a classroom project to motivate the students in the beginning of the studies of Power Electronics. The following projects are presented: electric and ignition automotive systems, solar car and fuel cells inverters. The second application is the design of a dc/dc converter with a non-linear controller for an engine electronic control unit. The SEPIC converter was selected based an easy attainment of positive and negative voltages.

The third application consists of the development and assembly of a PWM converter for FIRE engine cooling system. First was developed a model for the cooling system; this study became necessary since increased energy demand, longer life engine, greater control of engine performance and reduced emissions are priorities for engine manufactures.

Mentor Products: Analog mixed simulation, HDL-A, AccuSim

Bio:
Prof. Lauro de Vilhena Brandão Machado Neto (M'97 IEEE), was born in Parnaiba, Brazil, on November 4, 1960. He received the B.S.E.E. and M.S.E.E. degrees from Federal University of Minas Gerais(UFMG-Brazil), in 1985 and 1989, respectively.

In 1986, he joined the staff of the Electronic Engineering Department, Ponthifice University Catholic of Minas Gerais (PUCMINAS-Brazil), where he is professor of Power Electronics and Energy Systems and Coordinator of the Power Electronics Laboratory (LABEP-PUCMINAS).

In 1996, he works at FIAT Automobiles's Research Centre in Turim, Italy, in projects connected with the Agreement FIAT-PUCMINAS, Cooperation for Development.

His current research projects is in the area of PV systems and dc/dc converters for automotive applications.

Title: Expedition Library Manager Glitches & Workarounds
Author: Nick Barbin
Org: Optimum Design Associates
Contact: Nbarbin@optimumdesign.com

Abstract:
About a year ago ODA seized the opportunity to put together a new and fresh, fully integrated library for the Mentor Expedition Library Manger. The purpose of this library was to leverage ODA's experience in offering new users a quick and efficient way to start using their Mentor Expedition tool. While in the process of working on this new library, our librarians came across many little software glitches that required a work-around to complete the task at hand. ODA would like to share our experiences of these glitches but more importantly how to resolve them.

ODA currently uses the Mentor Expedition Pinnacle, Design Capture, and Library Manager products.

Bio:
Nick Barbin is president and co-founder of Optimum Design Associates (ODA), a printed circuit design layout and engineering service company. He has been designing PCB's for over 17 years in a service environment for many top companies within Silicon Valley as well abroad. In 1999, he received the highest score in the PC Design Magazine Top Gun contest and was inducted into the Top Gun Hall of Fame.

Title: Generating a PDF with Searchable Text from a Board Station Layout
Author: David A. Duncan
Org: Lockheed Martin Corporation
Contact: david.a.duncan@lmco.com

Abstract:
A recurring complaint among Mentor Board-Station users is the inability to export graphics from Layout to a pdf document with searchable text (the REFs show up in the exported postscript as a series of line-draw commands). While this capability is available for the new Expedition toolset, many are still using layout and will continue for some time. The paper presents a methodolgy using Ample scripting and perl scripting to solve this problem. It presents workarounds for the lack of font options in Layout and the inability to directly access the text information for the REF property. It also provides a "flipped" view of the back side of the board to match a user's view of a real PCB (instead of the standard Layout view of the back side as seen looking "through the board" from the front).

This paper not only describes the details of how to provide this functionality, but also describes a simple dialog-box interface for easy use.

Mentor Products: Layout

Bio:
David A. Duncan has been a Digital Designer for over 20 years, with experience in Board-Level Design as well as FPGA/ASIC design. Currently, a Senior Staff Engineer at Lockheed Martin in Orlando, FL, he has worked with Mentor tools for over 15 years both using the tools and writing userware to automate design tasks.

Title: Engineering and Manufacturing Collaboration in the Twenty-First Century
Author: Steve Chidester
Org: e4eNet Incorporated
Contact: steve.chidester@e4enet.com

Abstract:
As project schedules get shorter, project teams get larger, and supply chain partners become more geographically dispersed, a new problem faces product development teams -- how do you get the right people together (with the right data) to solve problems that inevitably arise during the development and manufacturing of complex electronics products? Most engineers and designers don't recognize the full the extent of this problem throughout the product development cycle because they only see the part they play in it. This is an educational presentation that focuses on board-level engineering and manufacturing collaboration and answers the following questions:

• What is the common design collaboration/communication process today, and what are its shortfalls?
• What is Engineering Collaboration, and how does it address the shortfalls/why is it beneficial?
• What are the types of collaboration available to be used:
  • Manual methodology
  • Home-grown automation
  • Collaboration solutions
• Summary of how the designer / company wins by using a collaborative process

Mentor Products: Board Station, Expedition PCB

Bio:
Steve Chidester is a Vice President at e4eNet, a company dedicated to solving engineering and manufacturing collaboration problems. Prior to joining e4eNet, he was the product marketing manager for Allegro and SPECCTRA at Cadence Design Systems for 10 years. He began his career as a schematic drafter at Sperry Univac and later became a printed circuit designer at National Semiconductor.

Title: Configuration of Extraction Deck for an N-Well CMOS Process
Author: Himanshu Arora (Presenter) and Dr. James Morizio
Org: Department of Electrical and Computer Engineering, Duke University
Contact: ha@ee.duke.edu; jmorizio@ee.duke.edu

Abstract:
Mixed-Signal design requires correct estimation of device and interconnect parasitics in-order to obtain a close co-relation between chip test results and simulation data. This paper introduces configuring Extraction deck for interconnect and device parasitics for an N_Well CMOS process in the Mask mode. The deck is calibrated with Mosis 31 stage ring oscillator for extracting the device parasitics namely Area of Source and Drain ( AS, AD); Perimeter of Source and Drain (PS, PD); Number of Squares of Source and Drain diffusion (NRS and NRD). The algorithm for PS and PD calculation, stated in Mentor Standard Verification Rule Format (SVRF) manual, was modified to allow usage of Area Calculation Method 3 (ACM) mode parameter in HSpice Model file. The presence of source resistance due to contact_to_active, Diffusion resistance and Substrate resistance ( p- epi) reduces transconductance (gm) of the transistor, leading to reduction in gain and Gain Bandwidth of the Amplifier. In consultation with Mentor Technical Support people it was found that ICExtractRC with release D of ICGRaph is not capable of extracting resistance due to epi ( p- substrate). The deck was also configured for extracting intrinsic, crossover and nearbody interconnect capacitances.

Mentor Products: ICgraph and xCalibre

Bio:
Himanshu: Graduate Student at Duke University. Did Undergrad. in India from REC Warangal in 1996. Was involved in Industrial R&D in Asea Brown Boveri and CMC India for around three years. Currently pursuing PhD at Duke University in Mixed Signal VLSI design.

Bio:
Dr. Morizio: Adjunct Professor at Duke University in Mixed Signal VLSI.

Title: FPGA on Board
Author: Bob Potock
Org: Mentor Graphics Corporation
Time required: 60 minutes

Abstract:
On average, there are approximately 1.5 FPGA devices on every Printed Circuit Board being designed today. These popular devices are huge both in terms of equivalent ASIC gate capacity and numbers of programmable I/O (millions of gates and thousands of relocatable pins). They also have very fast edge-rates in order to get signals on and off the chip as fast as possible inducing high-speed problems where board interconnect effects can no longer be ignored. Therefore signal integrity and timing closure of the FPGA on Board is becoming acutely problematical when every re-spin of the FPGA can result in very different timing and device pin out. This session will cover how the interconnect and timing closure problem is being addressed by Mentor Graphics in order to guarantee right-first-time FPGA on board design.

Bio:
Bob Potock is the Product Line Director for System Design Creation in the Systems Design Division. Mr. Potock has been involved in board based system and FPGA design through most of his career. Prior to joining Mentor Graphics, he held management positions in software/hardware engineering, marketing and field operations. He has over ten years of engineering and marketing management experience in the EDA industry working for companies such as AT&T Bell Labs, VeriBest, Cadnetix, NeoCAD, Intel and Unisys. A graduate of Case Western Reserve University, Mr. Potock received a B.S. in electrical engineering and is completing an MBA from Regis University.

Title: FPGA Advantage - Design creation, management, simulation & synthesis in one complete flow

Abstract:
This session will introduce the most powerful integrated HDL-based solution for FPGA design. This flow unites the multi-language, multi-platform design management capabilities of HDL Designer Series, for creation, reuse and management, ModelSim, the leading HDL simulation technology, and LeonardoSpectrum for advanced synthesis. You will also learn about FPGA BoardLink, the tool that automates the placement and wiring of the FGPA symbol within the board schematic reducing this process from days to seconds.

Title: What’s New and Cool with Board Station RE

Abstract:
This presentation will start with an overview of Board Station RE functionality, followed by a review of capabilities added in the latest releases.

Title: What’s New and Different in WG2000.5

Abstract:
Overview of functionality added in the WG2000.5 release. It will focus on Design Capture and Expedition PCB.

Workshops: (Sunday, February 24, 1:00-5:00 pm)

Title: FPGA Advantage - A complete design flow solution for multi-million gate FPGA design (hands-on)

Title: High-Speed Board Design (hands-on)