MUG 2000 Agenda

	Time	Program
	11:00am-6:00pm	CONFERENCE REGISTRATION
	12:00-3:00 pm	Steering Committee Lunch Meeting
	5:00-7:00 pm	Welcome Reception
	Time	Program
	7:30-8:30 am	Steering Committee Breakfast
	7:30-8:30 am	Conference Speakers' Breakfast
	7:30-8:30 am	Breakfast
	8:30-8:45 am	Opening Remarks Karen McConnell
	8:45-9:15 am	Mentor Graphics Welcome Wally Rhines
	9:15-9:40 am	Customer Support Remarks Tom Floodeen
	9:40-10:00 am	Monkey Reports
	10:00-10:15 am	MUG Appreciation Awards
	10:15-10:45 am	Break
	10:45-11:45 am	Keynote Speaker: Robert X. Cringely
	11:45am-12:45pm	University SIG Lunch Meeting
	11:45am-12:45pm	Lunch (with Analog SIG table)
		Circuit Design	Design Support	PCB Design	System Design
	12:45-2:15 pm	Ultra 3 and Calibre -Sun Microsystems Using Calibre-LVS for General SPICE Netlist Comparison - David Gradin		PCB Track Keynote - Henry Potts AutoActive Marketing Discussion - Charles Pfeil	Development of an FPGA-Based South Bridge Using Spectrum and ModelSim - W. D. Richard A Logic Simulation Benchmark Set - Roger Chamberlain Mentor Tools in the New Electrical and Computer Engineering Program at VCU -Robert H. Klenke
	2:15-2:45 pm	Break
	2:45-4:00 pm	IC SIG Meeting		PCB Q&A	Digital Voice Recorder : Thaitalk - Chumnarn Punyasai A VLSI Implementation of DES and Triple DES with Pipelining Technique - Ali Ziya Alkar Architecture Power Reduction in DCT processors - Hani F.Ragai
	4:00-4:30 pm	Break
	4:30-5:30 pm	IC Q & A	Library data on the Intranet: The LMS Toolkit and Beyond - Andrew W. Green Symbol Genie and Geom Genie Configuration at Marconi - Franz Crystal	A Review of PCB Manufacturing Formats and what they mean to you - Joe Morrison Creating External Formatters in SRP - Phil Lindberg	RF SIG Meeting
	5:45-6:45 pm			PCB SIG Meeting
	Time	Program
	7:30-9:00 am	Steering Committee Breakfast
	7:30-9:00 am	License SIG Breakfast Meeting		WorkFlow SIG Breakfast Meeting
	7:30-9:00 am	Breakfast
		Circuit Design	Design Support	PCB Design	System Design
	9:00-10:15 am	Teaching Full Custom Design using Schematic Driven Layout and the MGC ASIC Design Kit - Jim Frenzel ASIC Design Kit (ADK) - a Users Perspective - Karl Fielhauer	Userware SIG Meeting	Finite Element Analysis of Multilayered Boards - Dieter Haller RF Architect/Layout Custom c++ Shape Code - Russ Brown	QuickSim Pro celebrating the new millennium -Dina Atef Using QuickSim Pro to verify the CONTOUR SSR - Mary Harris Using QuickSim Pro for board level modeling of an 8051 Microcontroller - Mitchell
	10:15-10:45 am	Break
	10:45am-12:15pm	Extracting Accurate Simulation Measurements Using Eldo - Erasto Kashoro	Mobile Computing with the Mentor Board NT Environment - Steve Hersh NT Promises: Virtual or Real? - Tony Defina	Real World Routers - Karen E. McConnell Breakout Geometry - Pro's, Con's, and How-To's - Bruce R. Mayer	Synthesis of communication interfaces for heterogeneous systems using VSIA recommendation - Geneviève Cyr Should Your Company Attempt HW/SW Co-Verification? -Jim Kenney
	12:15-1:30 pm	Lunch at the Tradeshow
	12:15-4:00 pm	Tradeshow
	4:00-5:00 pm		Library SIG Meeting	Design Environment SIG Meeting
	5:00-6:00 pm			PCB Q & A
	6:30-8:00 pm	Steering Committee Dinner
	Time	Program
	7:30-8:30 am	Steering Committee Breakfast
	7:30-8:30 am	Breakfast
	8:30-9:30 am	MUG Business Meeting
	9:30-9:45 am	Break
		Circuit Design	Design Support	PCB Design	System Design
	9:45-10:45 am	Device Generators are Only the Beginning - David M. Zar Setting Up and Modifying ICdevice Variables for Schematic Driven Layout -Neil DeBella	Benefits of creating and using Electrical Board Descriptions (EBDs) with the ICX tools - Tom Rondeau	Board Design in a Global Company - Jan Sempels	FPGA/ASIC SIG Meeting
	10:45-11:00 am	Break
	11:00am-12:00pm	2.7 Giga Bytes per Second QuickSim II Table Models using Continuum Mixed Signal Simulator - Danny Flowers	Virtual Redundant Array of Independent Disks (RAID) with LINUX OS for Expansion of EDA Tools Platform - Lauro de V. B. Machado Neto DesignView Online Help and Design Overview - Angelique Herran	Board Level Timing Analysis in a High Speed Design Flow - Matthew Hogan	Why Invest in an Interractive WorkFlow System? - Bruce R. Mayer Migration to a VHDL-Based FPGA Flow - Phil Lindberg
	12:00-1:00 pm	Lunch
	12:00-1:00 pm	SIG Chair Lunch
	1:00-2:30 pm	Test Simulation with a VHDL PRML Design - Tom Chambers System-on-a-Chip High Speed Bus Architecture - Ed Suffern	Global Support in a lean corporate environment: User Support - Robert Meagher Global Support in a lean corporate environment: Infrastructure - Todd Bordner Support, Design Reveiw and Designing From Remote Sites Using Microsoft NetMeeting - Terry C Dickens	Implementing a Switch Fabric design in both the electrical and physical worlds - Jim Bell Printed circuit design challenges at 1 Gigbit/s and beyond - Scott McMorrow	Reducing electrical system design effort by automating design analysis - Nigel Hughes Cell Characterization for Analog Cells Reuse - Ahmad Helmy Top-Down Analog Design and Full-Chip Bottom-Up Verification with Analog Languages -Gary Pratt
	2:30-3:00 pm	Break
	3:00-4:30 pm	Implementation of Hot-Carrier Reliability Simulation in Eldo - Medhat Karam Macromodeling Dynamic Thermal Effects with SPICE - Matt Sprengeler	EDA Architecture Workshop - Gregory L. Smith	The best of the best, using IS and Expedition in a common environment - Steve Baker How to fully leverage symmetry in board level designs using the IS Floorplanner - Bernard Voss	FPGA Design Flow with FPGA Advantage - Homayoon Larki Using Altera LPMs and Xilinx Coregen parts in FPGA Advantage, Renoir, ModelSim, and LeonardoSpectrum - Paul Ree
	5:00-6:00 pm	New Steering Committee Reception
	7:00-11:00 pm	Mentor Graphics Party: Best Paper Awards
	Time	Program
	9:00am-5:00pm	Training Classes
	6:00-10:00 pm	Steering Committee Dinner & Meeting
	Time	Program
	9:00am-5:00pm	Training Classes