Abstract:

If we can count on anything, we can count on signaling rates going faster 
and faster for PC boards.  We know from our experience that when electrical 
signaling rates reach 1 GB/S and beyond on conventional FR4 based printed 
circuit boards, high-speed design, analysis and layout cannot depend on the 
standard rules of thumb. The rules have to change. This paper will discuss 
the implications of high signaling rates and how this will effect your 
board design cycle.  Specific attention will be placed on general design 
concerns, on analysis and simulation issues and layout challenges.

Bio:

Scott McMorrow: Principle Signal Integrity Engineer
Scott has been involved in Systems Design and Signal Integrity Engineer for 
over 20 years. He has extensive experience working with customers to solve 
their SI and timing analysis problems. Scott also teaches classes in Signal 
Integrity technology.

Stephanie Goedecke: Signal Integrity Engineer
Stephanie has been involved in systems design and SI Engineering for over 6 
years. Her systems and SI engineering experience includes video switches, 
and communications systems.

Schedule Restrictions: None