Abstract: 

This paper describes a method for improving time to volume for complex
mixed signal devices using Test Simulation technology.

Test Simulation is a methodology that allows an
engineer to develop the test program for a production tester with a model of
the device under test. The principal advantage in using Test Simulation
is to allow more tester programming to be completed prior to first silicon, 
enabling a shorter product development time. The paper describes
this and other reasons for applying Test Simulation, it reports on
the observed costs and benefits as well.

The observations are based on a advanced PRML product
development with which Test Simulation was applied.  A critical enabler
of a successful Test Simulation project is a fast top level model of
the chip. This requirement was met with a high level VHDL model of
the PRML chip.

The tester software environment passes stimulus to and
receives responses from the Modelsim PLUS VHDL chip model via
the Verilog PLI. The paper also provides an explanation of this
technology.


Bio: 

Tom Chambers is a VX applications engineer at
Teradyne.  Doug Matthes is a test engineer and Member of the
Technical Staff at Texas Instruments.