This paper will provide an overview of the changes and new features that will appear in the IEEE Verilog standard for 1999 in the context of the accurate simulation required for ASIC design. For over two years, three task forces (PLI, behavioral, and ASIC) have been working to update this standard. A brief overview of the PLI and behavioral task force efforts will be provided. The focus of this paper will be the new features developed for ASIC design by the ASIC task force, including new timing checks and extended VCD.

Bio

Steve Wadsworth - Steve has over 18 years of industry experience in test, design, and EDA tool management. He is currently the Manager of Library Development for American Microsystems, Inc. in Pocatello Idaho. He is the chair of the ASIC task force (IEEE 1364) and a member of both the VITAL TAG (IEEE 1076.4) and the SDF standards group (IEEE 1497).

Tom Dewey - After obtaining a BSEET degree from OIT, Tom has held various positions over the last 11 years within Mentor Graphics in the areas of modeling, synthesis, and verification. Tom was involved in the definition and deployment of VITAL, is an active member of the ASIC task force defining new Verilog features, and is active in the OVI working group that is defining the Design Constraint Description Language (DCDL). Tom is currently a Technical Marketing Engi-neer within the Strategic Partnerships and Alliances group, providing support for corporate deployment of EDA standards and for third-party design flow integrations.