This paper will provide an overview of an emerging standard from OVI - the Design Constraint Description Language (DCDL). This standard is gaining momentum and has garnered support from VHDL International (VI) and the SLDL effort as well as from the VSI Alliance. The standard's scope includes entire design flows covering timing, power, test, area, physical, PCB, and other constraint domains. The current focus of this standards effort is on the timing constraint domain. DCDL will be used for initial constraint entry, constraint interchange between tools, and IP authoring to express design intent.

Bio

Tom Dewey - After obtaining a BSEET degree from OIT, Tom has held various positions over the last 11 years within Mentor Graphics in the areas of modeling, synthesis, and verification. Tom was involved in the definition and deployment of VITAL, is an active member of the ASIC task force defining new Verilog features, and is active in the OVI working group that is defining DCDL. Tom is currently a Technical Marketing Engineer within the Strategic Partnerships and Alliances group, providing support for corporate deployment of EDA standards and for third-party design flow integrations.