The reuseability of IP cores is a critical factor in the speed and predictability of IP integration, and significantly affects the success of an entire SoC project. To allow a more rapid adoption of best practices for reusability, Synopsys and Mentor Graphics announced in June their intent to jointly created OpenMORE, a reference metric for reusability. OpenMORE is scheduled for first release at the IP 99 Edinburgh Conference, and will then be available to all at no charge.

OpenMORE includes the complete set of rules and guidelines of the original Synopsys Measure of Reuse Excellence (MORE) program, as well as the recently-released Reuse Methodology Manual (RMM) Second Edition, jointly-authored by Mentor and Synopsys. OpenMORE adds new measurability criteria for design and verification for soft, firm and hard IP, plus it incorporates key deliverables from the Virtual Socket Interface Alliance (VSIA) industry group. OpenMORE has been welcomed by the Virtual Compenent Exchange (VCX), Design and Reuse, and RAPID industry organizations as a practical approach to simply and quickly evaluate the reusability of IP cores.

Mentor Graphics and Synopsys will discuss the industry's need for an open reference metric for reusability, and provide an overview of the scope and content of OpenMORE. Additionally, Synopsys will discuss its IP Catalyst Web-based Catalog of MORE- and OpenMORE-rated IP cores referencing the 40+ independent IP companies that are committed to publish their ratings. Mentor Graphics will discuss incorporating the OpenMORE assessment program into its Inventra IP Infrastructure in order to offer the IP environment necessary to transfer OpenMORE-certified deliverables to the SoC environments of system companies. VCX will discuss the potential for use of OpenMORE in efforts to establish criteria for IP customers to use when procuring commercial IP cores on the Virtual Component Exchange.

Bio

Pierre Bricaud is the Director of Marketing for IP & Physical at Mentor Graphics and manages Mentor's Inventra IP Factory. Previously, Pierre was at Compass Design Automation where he was Director of Marketing for WW software products. Before Compass, Pierre spent 17 years in Philips Semiconductor and Signetics organizations in France, Netherlands and U.S. His last position with Philips was manager of WW ASIC Design Centers for Philips' ASIC division. Pierre has always been involved in leading edge techniques, methodologies and technologies evolving around ASIC-ASSP and IC design in Bipolar and CMOS semiconductor processes. Pierre is the co-author of the Reuse Methodology Manual, First and Second Editions.

Kevin Kranen is the Director of IP, Library and Timing Programs for Synopsys. His current responsibilities include leading Synopsys Synopsys initiatives with IP providers and library vendors, as well as driving consistent modeling and timing solutions within Synopsys. In his past 10 years of experience with Synopsys, Kevin has held a number of relationship management and product marketing roles, including product marketing manager for the launch of Synopsys' integration into the Falcon Framework. Prior to Synopsys, Kevin worked for 5 years at Daisy Systems as an applications engineering manager for digital design products. Kevin spent two years designing mainframe computers for Burroughs/Unisys preceding his experience at Daisy. Kevin has a BSEE and M. Eng. degree from Cornell University.