Virtex is a new FPGA architecture from Xilinx and within a short period of time it is being accepted by the design community as a standard miilion gate FPGA. There are several new architectural features in Virtex which the synthesis tool can take advantage of and one such feature is using the Virtex LUT (look up table) as a shift register. This is a very unique feature in Virtex we can implement a huge pipeline delay structure compactly in SRL which takes very less area when compared to the traditional mapping. This kind of structure is often used in DSP applications so designers doing DSP will benefit a lot from this. This paper will be on how spectrum uses SRL and will present some example designs and data.

Bio

With exemplar for last 2 yrs worked on diffrent areas ofthe tool timing, mapping etc. Before this I worked for Meta Software, Xilinx & Escalade.