Wednesday 09/29/99 8:30 - 10:00,   HDL Design


Optimizing VHDL, Verilog and Mixed-HDL Simulation Using ModelSim Performance and Coverage Analysis

Julian Medinger
Mentor Graphics Corporation, Model Technology Inc.
julianm@model.com


Abstract

The latest version of ModelSim (v5.3) incorporates two important new features:

-- The Performance Analyzer measures how each level of hierarchy in the design (down to each line of code) affects simulation performance.

-- The Code Coverage analyzer measures line coverage as the design and testbench are simulated.

These capabilities will allow users to tune their design and testbench for maximum simulation speed and testing effectiveness. The new features will be described in detail and demonstrated in the presentation.

Bio

Julian Medinger is a Technical Marketing Engineer with Model Technology. He has over 10 years experience in EDA, primarily in design verification. He recently joined Model Tech from Synopsys.