With the explosive growth of the Internet and wireless communication use and applications, and the constant demand for new features, designers are facing significant new challenges. These new data communication devices and third-generation cell phones combine cutting-edge feature-rich technology, a need for low cost and low power, and incredible time-to-market pressures.

In this paper, we outline an efficient and robust mixed signal design flow for fast implementation of System on a Chip (SoC) for telecommunications products. This methodology is recommended for managing large design teams to insure timely implementation and verification of complex mixed signal projects that require short design cycle, working first silicon, low production cost, and complex features. This methodology is fundamental for the implementation of the new generation of wireless and wireline voice/data communications products such as 3G W-CDMA, ADSL, cable modem, Gbit ethernet, ATM, etc. This flow also provides a versatile infrastructure that supports, links and unifies all design activities, be it digital, analog/mixed signal, or RF design. The success of this methodology depends on the extensive use of design automation and simulation tools, comprehensive functional libraries, structured design methodology, and the adoption of a top-down design strategy. This flow is based on IP reuse and allows for the transition from bottom-up verification to top-down design over a short period of time. With this methodology in place, future enhancements and design revisions can be achieved in a fraction of the time typically needed, and with a much higher probability of a successful first silicon.

The flow is based on the following:

* Extensive use of behavioral modeling for digital, analog/mixed signal, and RF blocks. This is done at the design conception stage and during architecture exploration. At this level, hardware behavioral description language are employed (VHDL, VHDL-AMS, Verilog, Verilog-A, HDL-A, C, ..., etc). * Digital blocks will be synthesized and implemented using digital IP, ASIC libraries, semi- or full-custom blocks. * Digital blocks will be verified for timing compliance, and delays will be documented and back annotated to the behavioral level description if it exists. * Analog and mixed signal blocks will be further translated into lower level functional blocks at the behavioral or macro level. * Transfer functions of analog, mixed signal and RF blocks can be described using a modeling language. For future compatibility and conformity, it is recommended that an IEEE approved modeling language be adopted (VHDL-AMS at the present time). This will ensure the preservation and reuse of valuable IP. These behavioral models can also be supplied to customers for use in system level simulation during chip implementation. VHDL-AMS is a bridge across digital, analog/mixed signal and RF domains, and provides a single paradigm for behavioral modeling. * Once low level behavioral architecture is completed, then device level implementation using the specified technology is attempted. In this stage SPICE-level simulation is used. * Once the entire design is complete, it can be simulated again using a mixed signal simulator. This simulator will insure that the SoC is functional and all the pieces work together as the designers intended. At this level to gain speed various circuit blocks can be simulated at various levels of abstractions. * Effect of layout parasitics can be introduced into respective blocks, and simulations can be repeated for blocks with marginal performance represented by their layout netlists, while other non-critical blocks are represented by behavioral description. * The RF section can be designed and verified efficiently in the frequency domain using a RF simulator. Once complete, macro models for LNAs, filters, mixers, oscillators, and PAs can be created automatically from IP3 and noise simulations. Then, the complete RF section and the baseband interface circuits is simulated together to verify the overall system-level performance. * Once the entire design is implemented in silicon, and if successful, all the building blocks will be archived in a library for future reuse (design IPs).

Bio