As HDL-based or mixed design environment is being used intensively nowadays among customers that are doing ASIC/FPGA or board designs, we introduce to them our new MGC netlister HDLwrite.

Although VHDLwrite continues to increase in popularity among customers desiring schematic design entry with language-based simulation, it suffers from the fact that it relies upon the EDDM database as a means of defining connectivity. In addition, VHDLwrite does not support VHDL-AMS, which is needed by the Analog/Mixed Signal tools. VHDLwrite also netlists neither Verilog nor Verilog-AMS. On the other hand HDLwrite will netlist both VHDL and Verilog using the same environment setting, and also in future releases it will netlist AMS extensions for both, so HDLwrite will complement EldoNet in providing a complete HDL/analog solution.

HDLwrite is a falcon Framework-based tool that uses SVC (schematic view compiler) which is the new Mentor Graphics API, that reads data directly from graphics database in DA and load a CDP (connectivity data port) database directly without loading the EDDM database or accessing it. So significant speed increases and more efficient use of memory are expected, especially for large designs that are highly hierarchical in nature.

HDLwrite will offer a new facility to QuickSim Pro in its future releases, as the current implementation of QuickSim Pro implements a netlisting scheme, which uses VHDL as the top level of the HDL portion of any QuickSim Pro simulation. With the Verilog portion of HDLwrite in place, QuickSim Pro may then be extended to include "Verilog on top", as well.

Bio

Ashraf Hosni works as a development engineer in Mentor Graphics Egypt . He is responsible of the development of the next generation of Mentor Graphics VHDL & Verilog netlisters (HDLwrite), while also supporting VHDLwrite. He was graduated from Ain Shams University, Faculty of Engineering, Computer & Systems Dept. with Very Good with honor degree in 1998. His graduation project was VCAD (VHDL Computer Aided Design), which is an EDA tool based on VHDL, he worked in the synthesis tool part for PLDs that takes the VHDL and generates BNF (Backas Nawar Format) JEDEC format. He is preparing now to get a master degree in CAD field.

Walid M. El-Nokrashy works as a development and Q/A engineer at Mentor Graphics since 1998, his responsibilities is supporting the already existing netlister VHDLwrite, and also developing the new VHDL and Verilog netlister (HDLwrite). Walid has a BSC in Computer & System Engineering from Ain Shams University at Egypt with Grade Distinction with honor.