Purpose of the paper is to explain the technology to enable the advanced level debugging capability through cross probing and cross highlighting in Packaged Power (. Using HDL as validation database, and IPC channels between capture, simulation and synthesis, the paper will show how it is possible to take a graphical representation, create an HDL cross reference table, validate through simulation, convert into RTL and or Gate (technology based) schematic and maintain a 3 level cross probing/cross highlighting capability. From a gate level schematic the user will be able to highlight the equivalent high level graphics (for example a flow chart diagram or a state machine diagram) and the VHDL or Verilog expression statement that generated the gate representation itself through an optimization process. The paper will also explain how a user can take advantage of this unique high level of debugging.

Bio

Paolo Spazzini has been with Mentor Graphics for last 9 years. He is currently a Field Marketing Manager for Renoir and Packaged Power products family after covering different roles in the sales and marketing organization. Before Joining Mentor Graphics Paolo was a system engineer with a major European Aerospace company (Laben/Alenia Space Systems). Paolo has a Ph.D. in Computer Science with the University of Milan - Italy.