Techniques to Improve Time-to-Market during Prototyping

As we enter the new millennium, most designs are becoming more complex and unwieldy. On the other hand, demand for faster time to market is indeed a reality.

Prototyping a new PLD design can be a dreadful experience if not planned. Streamlining the design process, using the optimum design tools and standardizing the process flow is the only way to guarantee a foolproof design in the shortest possible time frame.

This paper describes a systematic step by step approach for prototyping a PLD design using a case study. Commonly encountered pitfalls and their possible solutions are identified.

The case study focuses on our current design of the robot signature card for the semiconductor wafer handling robot and flat panel display robot. We have used Verilog and Altera Hardware Design Language (AHDL) to target the MAX 7000 series Altera PLD. Modelsim is used to simulate the design.

Bio

Ruturaj Pathak is a Hardware Design Engineer with Adept Technology. Ruturaj is responsible for FPGA, board and system level design, including the layout and testing. Ruturaj holds an MSEE from Santa Clara University, USA and BSEE from D.D. Institute of Tech, INDIA. His technical interests are in high speed logic and board design. His hobbies are playing chess, astronomy and travelling.