Making Calibre LVS behave exactly like Dracula on legacy designs can be a challenge when the Dracula mosfet size tolerance for length and width was set to 0%. Chips containing critical analog circuits are at times verified to this exacting standard. Such cases typically depend upon the source netlist sizes being expressed in 0.00 micron resolution (that is, hundredths of a micron) because Dracula internally limits mosfet Length and Width values extracted from layout to that level of resolution. Calibre, on the other hand, calculates length and width to a floating-point resolution that is limited only by the hardware on which it is running. This means that any length and width data which Calibre extracts from layout must also be exactly hundredth-micron resolution, otherwise the size check will fail. This is an unnatural situation, since the layout data itself is normally formatted to 0.000 resolution, and when mosfets incorporate bent gates, the calculated effective width and length may be irrational numbers. We explain how to allow Calibre to verify such designs without spurious errors.

Bio

John Bartholomew has been employed since June 1998 as an Application Engineer in the Austin office of Mentor Graphics, supporting the Physical Extraction and Verification line of tools. Prior to that he worked at Motorola for 12 years in the areas of hierarchical verification, layout automation, and various aspects of physical CMOS IC design. When in the Portland area, he prefers to play hooky and sample the variety in the downtown brewpubs.