Our primary FPGA vendor supplies a macro generation package, called ACTgen, which makes it faster and easier to create large, data-path designs. We took advantage of the fact that ACTgen also supports a behavioral VHDL output file format and developed a process that uses Renoir to interconnect these behaviorally described "components" to create more complex VHDL models of sub-systems. This presentation describes our process and identifies the benefits we obtained by adopting it as an alternative design practice.

Bio

Mary Harris works for the Johns Hopkins University Applied Physics Laboratory as a member of the EDA tool support staff. She applies the knowledge gained from her 15-year career in circuit design and CAE tool support, to the development of hardware design processes using recent advances in design and verification techniques. Mary received a B.S.E.E. from the University of Maryland and a M.S. in Electrical Engineering from Johns Hopkins University.