We are developing an Integrated Electronics Module for spacecraft core electronics that uses a serial backplane data bus. Signal integrity issues in the complex transmission line structure formed by multiple daughter cards plugged into a common mother board limited our initial expectations to only supporting a data rate of 25 Mbits/sec using TTL signal levels. By using Mentor Graphic's IS tools and an emerging differential signaling standard (TIA/EIA-644, commonly called LVDS) we hope to be able to achieve data rates beyond 100 Mbits/sec. IS will let us layout and analyze a motherboard that implements a differential transmission line with appropriate characteristic impedance. IS will also permit us to model the effects of daughter card layout, edge connectors, and transceiver I/O impedance. Rather than build a single prototype system based on our engineering judgement, we will use IS to study alternative issues including parts selection (transceiver and connector), board layout and construction, and logic partitioning. Finally, the results we obtain from our IS simulations will allow us to establish realistic speed requirements for a rad-hard transceiver for our application.

Bio

Martin Fraeman has worked at JHU/APL for the past 18 years and has an SM from MIT. His work includes satellite architecture development and ASIC design. He also teaches a graduate course on VLSI Design in the Hopkins Part Time Engineering program.