For the last several years I have been encouraging my students to employ a top-down design methodology when coding for synthesis into FPGAs. The process begins with a pseudocode description of an algorithm that satisfies the problem specification. From the psedocode, a datapath is extracted that contains all of the necessary operators and data interconnections. This datapath is described via a block diagram that identifies all control and status lines between the datapath and a controller. The next step in the process is to develop a finite state machine (FSM) representation of the control logic that accepts external inputs and status inputs from the datapath and produces external outputs and control outputs for the datapath. At this point, an EDA tool such as MGC Renoir could be used to enter the design and generate synthesizable VHDL. However, I am hesitant to introduce too many tools in one semester. Furthermore, many of our courses are videotaped and offered through a distance education program which discourages the use of GUI tools. Instead, the students code by hand the FSM and datapath at a register level, resulting in numerous components and many signals. In theory, this should be a straightforward procedure, but from my experience the students typically do not fully understand their design, and thus waste an enormous amount of time re-writing and re-compiling the code in the process of debugging their design.

As an alternative, I have started introducing the concept of a FSM with Datapath (FSMD), originated by Gajski [Principles of Digital Design, 1997]. A FSMD description, represented in a tabular or graphical manner, is a compact and efficient mechanism for specifying both control and datapath functionality. Of particular interest to educators is that the FSMD may be easily translated into synthesizable VHDL, either manually or via a program. In this paper I will cover the basic feature of an FSMD description, the limitations, choices for coding VHDL representations, and the effects on synthesis. Finally, a comparison will be made between this approach and behavioral compilers, such as MGC Monet.

Bio

Jim Frenzel is an associate professor of Electrical Engineering at the University of Idaho. In a former life he was a Staff Engineer with the IBM Corporation in North Carolina. He is Ex Officio Chair of the MUG University SIG, second in popularity to only HJP, and has recently taken up the trumpet, much to everyone's dismay.