For a VLSI design course to be effective, standard VLSI topics must be combined with state of the art design tools. At the University of Alabama in Huntsville, several Mentor Graphics tools are used in the senior level VLSI sequence. In the two semester sequence, the students are exposed to various methods of IC design: full custom design, schematic driven layout and an HDL with synthesis approach. The students design a digital ASIC in the first semester and test the fabricated chips in the second. Students work in small design teams throughout. The first several weeks are devoted to learning all the tools required for a schematic based standard cell design flow using the Mosis Design Kit (MDK). By the end of the first semester, each design team submits a tiny chip for fabrication. The students then learn a synthesizable subset of VHDL. Several designs, including their MOSIS chip design, are modeled in behavioral VHDL, simulated and synthesized to Altera CPLDs. To aid in testing the MOSIS chips, a customizable test board was developed which contains several in-circuit programmable CPLDs and a socket for the MOSIS chip. Before the MOSIS chips arrive, each design team customizes their test board by making wire wrap connections, programming their design into one of the on board CPLDs and writing test software to drive the inputs and read the outputs across the ISA bus. In this way, the software written for the CPLD can be used to test the MOSIS chip.

Bio

David Hyde is part of the Digital Systems Design Team of the Computer & Data Systems Group at NASAØs Marshall Space Flight in Huntsville, Alabama. He is also a Ph.D. student at the University of Alabama in Huntsville (UAH). Rhonda Kay Gaede is an assistant professor of Electrical & Computer Engineeering at UAH. She teaches courses in VLSI design and test, computer architecture and computer programming.