Monday 09/27/99 1:00 - 2:30,   HDL Design


A General Co-Simulation Model on Seamless for Teaching H/S Co-Design

G. Bois (presenter), I. Campagna, J. Baillairge
Ecole Polytechnique de Montreal
bois@vlsi.polymtl.ca


Abstract

This paper describes a co-design experience in a MSc and PhD degree course at Ecole Polytechnique de Montreal. The architecture consists of an i960 processor, RAM for program and data, and an application specific coprocessor. Processor and co-processor communications (H/S interface) are based on two mechanisms that can be viewed as library Bio

Guy Bois received his B.S and Ph.D. degrees in computer science from the University of Montreal. He is currently Professor in the Department of Electrical Engineering at Ecole Polytechnique de Montreal. His interests are VLSI CAD and digital circuit design.