Yesterday's methodologies are no longer adequate to meet today's high speed PCB design challenges. Engineers must now deal with many signal integrity and timing issues early in the design cycle to avoid costly and time consuming design - analyze - iterate processes.

This paper presents a pre-layout analysis case study of the AGP 4x bus. There were several compelling reasons to do pre-route characterization on this design:

1) High speed source synchronous bus. 2) Minimal timing margin. 3) Minimal skew margin. 4) Differential and non-differential signalling. 5) Internal bus timing pushout effects. 6) External noise effects. 7) 2 routing layer constrained design.

The presentation will first discuss the problems suspected with AGP4x bus systems, followed by the method used to perform pre-layout analysis, and a brief review of the results. The presentation will complete with generalizing the results to other high speed busses, emphasizing the need for pre-route characterization.

Bio

Jim Bell currently works as a Signal Integrity Engineer for SiQual, Incorporated, a high speed digital design consulting firm serving North America and the Pacific Rim. He is currently a contractor within the Interconnectix Business Unit of Mentor Graphics, where he provides technical assistance regarding high-speed board design. A graduate of Northern Arizona University with a BSEE, he has over 10 years of real world experience designing high speed digital signal processing and computer systems.