Accurate device modeling is essential for simulation of high speed interconnnect timing and signal integrity simulation.

Attendees will learn about new and advanced EIA IBIS features such as package models, Electrical Board Description (EBD) models, multistage driver schedules, and dynamic over/under shoot limits that are required for accurate modeling of current and future generations of processors, modules and chipsets. Examples, applications, and simulation results of these and other IBIS features, will be examined. A brief review of IBIS fundamentals will be presented as a refresher. This workshop, an intermediate/advanced topic, is a follow on to the Basics of IBIS Modeling, presented at MUG 98 and PCB Design Conference East 1998.

Bio

Kim Owen has over 20 years of electronics industry experience, including high speed design, device modeling, and signal integrity analysis. Kim is a frequent presenter regarding IBIS modeling, including PCB Design Conference East 1998. As a current member of Mentor Graphic's Interconnectix Customer Success Team, Kim provides direct technical assistance, training, and consulting to Interconnectix users on a wide range of high speed design topics.