For detailed critical path analysis of an ASIC core, it is necessary to have the capability to selectively extract specific layout nets. This paper describes four different selective net extraction methods using both hierarchical and flat verification tools from Mentor Graphics. The run-time comparisons between the four results clearly indicate the value of data reduction and hierarchical processing. The extraction results were used in a circuit-level simulator and compared with actual silicon measurements.

Bio

David Gradin is a staff design engineer with LSI Logic in Gresham, Oregon. He is part of a memory design group working on both compiled and custom memory designs. Prior to joining LSI Logic, he worked for Mentor Graphics in Wilsonville, Oregon as a design methodology engineer and at ELDEC Corporation in Lynnwood, Washington as an ASIC designer. David holds a B.S. in Electrical Engineering from Portland State University and an M.S. in Electrical Engineering from University of Washington.