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Raghu Rao
Exemplar Logic Inc.
Fremont, CA
Exemplar Logic's Leonardo Spectrum can be used for ASIC synthesis today. The next release of the ASIC solution will have full support for the Synopsys .lib format, hierarchical timing analysis and timing optimization. The objective is to be able to produce an optimal solution that meets the designers timing constraints using minimum area for any given ASIC technology for which a .lib format library is available. The optimization algorithms are linear in nature, enabling fast and accurate synthesis. This enables designers to try out a variety of solutions, in limited amount of time.
ASIC library vendors will have a clean flow to qualify their ASIC libraries with Leonardo Spectrum. This will make available a number of ASIC libraries that have already been developed in the Synopsys .lib format.
With complete and accurate support for the .lib format library and with fast and efficient algorithms for optimizing area and delay, Spectrum provides an excellent opportunity for ASIC designers to get their designs done, and all this on their laptops or desktop PCs very quickly.
Bio:
Raghu Rao is the Director of Engineering at Exemplar Logic where he has worked for 4.5
years now, contributing to engineering first as a senior member technical staff, and then
as an engineering manager developing a hierarchical timing engine.
Raghu got his bachelors degree in electrical engineering from Mysore university and his masters in computer science from Hyderabad University, both in India. He worked for Texas Instruments for about 4 years, before moving to Logic Modeling Corp for a year and a half, after which he joined Exemplar Logic Inc.