Handling Complex Clocking Schemes with the SST Velocity Static Timing Analyzer

Dan Milliron
Mentor Graphics Corporation

The SST Velocity product simplifies the specification and analysis of complex clock circuits. This paper describes how ASIC designers can use the SST Velocity product to analyze asynchronous clocks, merged clocks, multiplexed clocks, divided clocks, gated clocks, internally generated clocks, virtual clocks, and temporary clock trees.

Bio:
Dan Milliron is the lead engineer in the SST Velocity product engineering group. Before joining Mentor Graphics Corp. in 1992, Dan worked ten years as an ASIC designer for Tektronix, Inc. and for a video engineering company. He has a BSEE and a BSCS from MIT.