Tips and Tricks in Writing VHDL for Synthesis

 Doug Perry
Exemplar Logic, Inc.

Creating a design in VHDL can streamline the design process tremendously if done properly. Designers can learn the syntax of VHDL fairly quickly, but learning the best way to create a design for synthesis takes more time. Designers typically run into a few style problems when just getting started that can significantly impact schedules the first time through. This talk will describe a method of setting up a design and writing the VHDL code that can help solve some of these problems.

Bio:
Mr. Perry received his BSEE from SDSU in 1978, and completed an MSCS at U of Santa Clara in 1981. He has been working in industry since 1978. Mr. Perry has done hardware design, software design and application engineering work for over 19 years. Mr. Perry has worked at Data General doing NMOS chip design, Calma, Daisy, and Vantage doing software design and Synopsys, Redwood Design, doing application engineering work. In his latest position Mr Perry is Manager of Training and Consulting at Exemplar Logic where he helps customers with advanced training, manages class material creation, manages training activities, and manages consulting activities.