As the size of FPGA devices is getting bigger and bigger, it is getting difficult and time-consuming to create and maintain a design-specific FPGA symbol. Specifically, it is difficult for a designer to create an FPGA symbol and manually map its I/O pins to signal names when the device has more than 200 I/O pins. It would be desirable to have a mechanism to automatically produce an FPGA symbol from the output of the FPGA Place and Route tool. This paper discusses a way to create an FPGA symbol and mapping files from the output of Altera's MaxPlus II place and route tool. The automatically generated symbol is mapped to a Synopsys model for simulation and to a Boeing geometry for board layout. This approach provides a symbol that represents the functionality of the final FPGA, reduces human error during creation and maintenance of the design-specific FPGA symbol, and minimizes maintenance of the FPGA symbol and schematics it is used on after each revision of the FPGA I/O.

Bio:
Michael A. Pringle is a Principal Engineer with Electronic Computing Support organization in Boeing IS&DS Group. He has worked for the Boeing Company for 24 years, and has been supporting board-level design with Mentor Graphics libraries and tools since 1985. Chul-Ho P. Chang is a Sr. CAE Application Engineer in the same organization with Michael. He has worked for Boeing Company for 14 years as a digital simulation specialist. His responsibility includes digital simulation support in various Boeing programs, FPGA and Gate Array design, and a VHDL-based design process study. Prior to joining Boeing, he worked for E. F. Johnson Co., as a Signal Processing Design Engineer.