CPLD/FPGA Tools-Oriented Design Process

Ken Frick
Lucent Technologies, Bell Laboratories
kfrick@lucent.com
303-538-4707

Sometimes it is useful to discuss what is, or what may be, obvious. The CPLD/FPGA design process presented in this paper does not seem to be novel, at least not to the author. The process was derived, largely, from the functions and capabilities of tools available for programmable logic design. This paper will describe the process used at the Business Communications Systems (BCS) division of Lucent Technologies, Bell Laboratories, in Denver. The process fundamentally involves these activities: * Design capture- Top-Down, VHDL, using Renoir; * Functional simulation- VHDL using VSystem/ModelSim; * Synthesis- using Leonardo/Galileo Extreme; * Fit/PAR- using vendor tools; * Timing simulation- using VSystem/ModelSim; * Hardware verification- In the target system. Details about process steps will be given along with the reasoning behind our choice of tools. A key objective of this paper and presentation is to stimulate a discussion and exchange of ideas, among session participants, relating to CPLD/FPGA development processes and tools. The hope being that, as a result of the discussion, each participant will find ways to improve their own development environment. So, come prepared to be involved in this session.

Bio:
Ken Frick is a Member of Technical Staff at Bell Laboratories in Denver. He works in a hardware development organization and does both board-level and programmable logic design. Ken received a BSEE from Northern Arizona University in 1979 and an MSEE from the University of Colorado, Boulder, in 1981.