A Design Flow for Mixed Schematic Capture/Logic Synthesis Based Design with Actel FPGAs

Robert H. Klenke
Virginia Commonwealth University
klenke@Virginia.EDU
804-924-6079

The paper will describe a design flow for developing Actel FPGAs using the Mentor Graphics and Actel tool sets. Behavioral HDL descriptions, logic level synthesis, schematic capture, and graphical HDL generation techniques are used where most appropriate to enable fast, efficient design of complex digital systems. Extensive simulation of virtual prototypes is performed at each stage in the design process to verify the design as each step is completed. A complete example of using this design flow to implement a simple 8 bit multiplier on a single FPGA will be presented. Although the example presented uses VHDL as the HDL of choice, all of the tools used support Verilog and thus it could easily be used in this design flow.

Bio:
Dr. Robert H. Klenke has just recently joined the faculty of the new School of Engineering at the Virginia Commonwealth University. Previous to that, he was a member of the research staff of the Center for Semicustom Integrated Systems at the University of Virginia. Dr. Klenke received his B.S. degree in Electrical Engineering from the Virginia Military Institute in 1982, and his M.S. and Ph.D. Degrees in Electrical Engineering from the University of Virginia in 1989 and 1992, respectively. His research interests include system level modeling, hardware description languages, parallel algorithms for automatic test pattern generation, and high speed digital design.