A Study of Fastscan Transition Fault ATPG Capability for Microprocessors

Dr. Nandu Tendolkar and Rajesh Raina
Motorola
nandu@ibmoto.com
512-424-8392

Microprocessors designers have achieved over 95% stuck-fault test coverage by using DFT techniques and stuck-fault test pattern generators to generate the test patterns. This has contributed to improvement in chip quality. However, faults that affect the timing of the circuits, transition or delay faults, escape the stuck-fault tests. Further improvement in quality of microprocessor chips will depend upon our ability to detect the transition faults. This paper distinguishes between transition and delay fault models with the use of simple examples. We define the DFT capabilities that are required for facilitating at-speed transition fault test generation for microprocessors. We present our experience with Fastscan (tm) in generating transition fault test patterns for PowerPC microprocessors, including the PowerPC 750. The paper emphasizes practical design considerations such as clock distribution and skew management that are needed for proper implementation. We also discuss enhancements required to improve transition fault test coverage. Fastscan is a trademark of Mentor Graphics Corporation. PowerPC and PowerPC 750 are trademarks of IBM Corporation.

Bio:
Nandu Tendolkar Dr. Tendolkar is a Senior Engineer at IBM Corporation in Austin, Texas. Currently he is responsible for the Design for Test of PowerPC Microprocessors at the Somerset Design Center. At IBM, he has done research work in built-in self test, delay test, error detection and fault isolation, and high availability system design. He has received an IBM Outstanding Innovation Award for his work on 308X diagnostics and has two patent applications on file and holds one patent. He was an Adjunct Professor of Computer Science at Marist College, Poughkeepsie, New York from 1981 through 1995. Dr. Tendolkar received his B.S degree in Mechanical Engineering from Indian Institute of Technology, Bombay, India, M.S in Operations Research from Cornell University, Ithaca, New York and Ph. D. in Computer and Information Science from Syracuse University, Syracuse, New York. He is a Senior member of the IEEE. Raj Raina Raj Raina, a Principal Scientist with Motorola, currently manages the Design For Testability Department at Somerset Design Center in Austin, TX. Somerset is an alliance between IBM and Motorola to provide effective, state of the art PowerPC microprocessors with emphasis on time to market. Raj actively works with EDA industry towards the development of tools & methodology for effective testing & verification of very high-performance, deep sub-micron VLSI designs. Raj received his PhD & MS degrees in Electrical Engineering from Duke University and Michigan Tech. University respectively. He received his B.Tech with Honors in Electrical & Electronic Communication Engineering from IIT, Kharagpur in 1984. Raj is a member of IEEE & Sigma Xi.