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	Conferences SIG Info LUG Info FAQs Jobs Mentor Graphics MEMBERS ONLY Change Profile Email Archives SIG Top Issues User Library Conference Proceedings		1998 Abstracts and Bios by Track General Sessions Getting You Ready for Year 2000 Colleen Shannon and Jasjit Singh Design Environment BIG S/W Management at a BIG 10 Institution David L. Nelson A Work Flow Driven Concurrent Board Process R.D. Friesen and M.M. Escobar Managing IC Design Files in a Mixed NT and UNIX Environment Dave Hitz Avoid Problems When Defining Initial Workflows Nathan E. Lipke Process Definition and WorkXpert Design for PCB Development Chuck Vroman Using FLEXadmin for Software Usage Monitoring John R. Dozsa Automated Creation of FPGA Symbols from FPGA Place and Route Michael A. Pringle and Chul-Ho P. Chang Getting the Biggest BANG from Your Software Buck Rich Mirabella Using Mentor tools in a Mixed UNIX/NT Environment Bruce Swanson Improving Interoperability through S/W Licensing and Standards Adoption Kent Moffat Y2K Panel and Discussion Mentor Graphics Corporation Licensing Panel Mike Frison, Chris Burger, John Wallick, and Rich Mirabella PCB/MCM Design An Implementation of LMS/PDS at Raytheon Electronic Systems James Garretson Introduction to CFPI(Catalog File Procedural Interface) Bruce R. Mayer Are We There Yet? Physical Design Re-Use in the Mentor Graphics Toolset Andy Green Using MGC Variant Properties to Create Manufacturing Data Leo Dabbs and Mark Baker Modular Design Re-Use (Canceled) Gaylyn Johnson Reduce Cycle Time and Improve Quality through the Use of Modularity (Canceled) Russell Fett Design Evolution of Heatsinks Emmanual Galima Electrical/Mechanical Design Integration: An Introduction to IDF 4.0 and What It Can Do for You David J. Kehmeier Creating ICX/IBIS Models From XTK Models Using qd2ibis Kim Owen Practical Considerations in the Use of the 3D Mechanical Interface Walt Beltz Correlating Timing Results between the Charter and the Timing Sheet with ICX Marty Fouch Analyzing Signal Quality with IS Dan Lake Automated Printed Wiring Assembly (PWA) Producibility Analysis Gregory L. Smith Using MGC variant properties to create manufacturing data Leo Dabbs and Mark Baker Using BoardStation to Design a PCB with Buried Resistors Bob Sterrett Microvias into the Millennium Larry W. Burgess Silicon Design A study of Fastscan Transition Fault ATPG Capability for Microrocessors Dr. Nandu Tendolkar and Rajesh Raina A Design Flow for Mixed Schematic Capture/Logic Synthesis Based Design with Actel FPGAs Robert H. Klenke ASIC Design Flow from System Specification to Chip Karl U. Shenk CPLD/FPGA Tools-Oriented Design Process Ken Frick Comparing IC Chip versions Made Easy with IC Rules and Custom AMPLE Michael Tedeschi Using Continuum in TriQuint's Mentor v8.x Design Environment for GaAs ICs. Marty Zimmer Exemplar Logic Introduces LeonardoSpectrum (tm) The Modular Synthesis Solution Tom Feist Desktop ASIC Synthesis Solution Raghu Rao Tips and Tricks in Writing VHDL for Synthesis Doug Perry Calibre/xCalibre Overview Roy Dunn xCalibre Robert Todd IC Layout Technical Product Overview Janet Peterson Handling Complex Clocking Schemes with the SST Velocity Static Timing Analyzer Dan Milliron Static Timing Technical Overview Dan Milliron IP Shortens Time to Market and Enhances System on Chip Design Mentor Graphics Corporation System Design Application of Board-Level Simulation for Telecom. Switching Machine Design Il Seong Development of an 8051 Behavioral Model James F. Frenzel Modeling Analog Parasitics in a PCB Schematic Bill Bacher Modeling and Simulation of a DTMF Receiver Fabio Kurt Schneider HDL-A Application: PTC Thermistor Model Matt Sprengler Understanding and Solving Convergence Problems with the Accusim Simulator Tim Erlenmeyer QuickSim Pro: Under the Hood Paul Shupe Analog and Mixed Signal Extensions to VHDL Ken Bakalar A Strategic Process for System-Level Verification Janick Bergeron Automated Creation of FPGA Symbols from FPGA Place and Route Michael A. Pringle and Chul-Ho P. Chang Using ASIC/FPGA Models in Board Level Simulation Hugh J. Blair and Clifford E. Kimmery University & Research VHDL as a High Level Programming Language: Teaching Digital Design and Synthesis to Computer Science Majors Dr. Richard Spillman Effective Use of Mentor Grapics Tools in IC Design Course Rama K. Vedachla Project Specific Workflows and Their Application Shannon K. Kuntz and Dr. Jay B. Brockman Developing an FPGA Workflow to Ease Novice and Experienced Designers David E. Taylor and David M. Zar 4 Moduli Binary to RNS and RNS to Binary Conversion Eep M. Setiaarf and Pepe Siy Teaching Digital Testing Using Mentor Graphics DFT Tools Samiha Mourad Effective Use of Mentor Graphics Tools in IC Design Course Rama K. Vedachalam Marketing Closing the productivity gap for the Analog/Mixed-Signal Engineer: Capturing Reusable Design Expertise with VHDL-AMS and Verilog-AMS Ariel Cao Virtual On-Site Support - A Process Improvement Celeste Johnson and Mark Wheeler Inside the new Geom Genie version 2.1 George Opsahl Symbol Genie -- fast specification correct symbols George Opsahl ModelSim and Today's Changing Mix of HDLs Jack Woida ModelSim and Today's Changing Mix of HDLs Valerie Rachko SST Velocity Ravi Sekhar Best Practices for Increasing Flow Prototype Success Jordon Weddle ViewWare Andy Wilcock Methods to find, fix, and prevent signal integrity and timing problems in high-speed digital board design. An update of the ICX product line. Fred Cohen Hardware-Software Co-Verification Jim Kenney Monet: Architectural Exploration Through Behavioral Synthesis Aaik VanderPoel
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