Lateral high-voltage CMOS transistors are self-enclosed, round structures. The high-voltage drain area is in the center of the layout and is separated from the low-voltage gate and source sections through a lightly doped drift region. The gate and drain interface requires rounded corners to reduce the peak electric field and enhance the breakdown.

Every high-voltage transistor is a custom structure, and because of the complicated nature of these structures (for example circular patterns and custom drift regions). They are typically drawn manually. In standard VLSI CMOS technology, similar structures can be made that offer high-voltage properties. CMOS-compatible high-voltage NMOS transistors use the N-well junction for the drift region while the high-voltage PMOS devices use the P-Field junction for this purpose.

Using Mentor Graphic tools, we have developed a set of user-defined algorithms that automatically generate the layout for these structures. These algorithms were written in AMPLE for use with IC chip layout. They were extensively used for making the TARP (Transistor Array Research Project) chip. In this paper, we disclose the details of the these algorithms and show examples of their use.

Bio:
Thomas VanEaton is a MSEE candidate at Washing State University. He received his BS degree from WSU in 1994 and then worked for Lattice Semiconductor for a year before returning to WSU. Currently, he is doing research in high-frequency and high-voltage CMOS design. Areas of interest include analog circuit design and device physics.