This paper describes the experiences of a first-time instructor using Mentor Graphics tools to teach top-down VLSI design. Students in ECE474 VLSI System Design at Oregon State University proceed from a written requirements document to IC layout in 9 weeks. The main focus of the class is to impart a top-down design strategy using VHDL for design description.

Bio:
Roger Traylor is an Instructor in the Electrical and Computer Engineering Department at Oregon State University. Since August 1996, he has been primarily responsible for supporting the departmental CAD environment. His secondary role is to help students and faculty efficiently use industrial strength CAD tools. As such, he spends much time developing tutorials, teaching courses and helping in laboratories. Prior to this adventure, he worked for nine years at Intel Corporation.