Self checking devices will play an important role in ASIC verification. The methodology anD design tools are beginning to mature providing an alternative to traditional test solution. Some of the major benefits with BIST compared to a conventional scan design are the possibility to test devices in the field and the simplification of manufacturing test.

This paper presents our experiences using BIST technology in our most recent research project. The goal was to implement a real-time operating system in hardware and to use state-of-the-art tools for verification. The des ign is implemented using VHDL, consists of 200K gates and is built up by hierarchical standard cell blocks in conjunction with several internal RAM megacells.

We also presents our BIST flow and scripts used with the Mentor Graphics tools LBISTArchitect, MBISTArchitect and BSDArchitect. The results are viewed in terms of fault coverage and area overhead using BIST compared to a scan solution.

Bio:
Johan Starner and Joakim Adomat received their Bachelors degree in computer engineering from Malardalen University in 1994, and they are currently working as PhD students at the Multiprocessor Real-Time Architecture Laboratory. The research is focused on hardware architectures for real-time computer systems and design methods for ASIC design.