As design complexities increase and design cycles decrease, design reuse and the use of Intellectual Property become critically important in getting the product to market. But what language was the previous design written in? What format is the IP available in? Which HDL are the designers comfortable with? With ModelSim it isn't a concern. Come learn how the leading VHDL simulator extends it's technology to equally support Verilog for a seamless mixed-HDL simulation environment.

Bio:
Valerie Rachko is a Marketing Manager for Model Technology Inc., a Mentor Graphics Company. In preparation for her Marketing Manager role, Valerie worked for the past 7 years as a Technical Marketing Engineer for Mentor Graphics supporting VHDL and Verilog simulation tools. Prior to working in the EDA industry, she worked as an ASIC designer of navigational devices in the defense industry for more than five years. Valerie holds both a BSEE and a MSEE from Fairleigh Dickinson University in New Jersey and an MBA from Seton Hall University.