The intent of this paper is to provide an alternative method for Mentor PCB designers to reduce design layout cycle time. Doing this demands consciousness of a series of specific events and milestones. It is essential to define, execute and verify the steps to assure they are met along the way.

The key concept is that more than one layout person is working on the design at one time, they are working in a copy of the original container. Their assistance can be used for all aspects of the design cycle, from schematic capture, placement and routing, to drawing generation.

"Concurrent engineering", for us this is not just a buzzword, this is a method of absolute concurrent board layout design. Being in the competitive disk drive industry, time is of the essence, our livelihood depends on our beating our competitors to market. Occasionally, for circumstances beyond our control, we need a board out in half the time that it takes to do the job.

Regardless of the reasons why we may be given an unrealistic schedule, we are required to do what ever it takes to make it happen. So sharpen your competitive edge and learn from other users who have realized significant successes as we share our effective methodology to employ concurrent board layout design.

You can utilize this concurrent engineering concept at any stage of the design, from schematic input, to placement, or routing. We use two, three, but never more than four, layout people working simultaneously together. The circuitry is divided between the designers, hopefully your circuit can easily be broken into differing functionality for ease of separation. Each designer works in their own copy of the container, inputting just their own portion of schematic entry. After schematic capture is complete, all schematic sheets are all brought into one master design container. This can be done by copying in schematic data from different design container sheets in DA, Mentor is smart enough to not make duplicate instances when copying schematic data. After package is complete, back annotate and merge.

It is essential to take time now, to floor plan effectively for placement, taking into consideration components, routes, and power signals. Add boundary lines on the board for placement segregation, then create copies of the master design container and each layout person works in their designated areas placing parts (the dividing lines are just estimates of area required, the borders will require finessing). After placement is complete, all designers back-annotate and merge into their own respective containers. These merged schematic sheets that are now retaining the component locations and rotations will have to be recopied into the master design container in DA again. Then package, and create a startup file for layout, so every time it is invoked everyone will have the exact same defaults to start from. Make copies of the master design container again.

Now routing can begin, each designer routes the signals that enables them to stay in their own designated area when possible, bus signals that need to run for greater lengths (beyond your partitioned area) need to be analyzed and routed to a designated location where they will be completed later. About every 90 minutes stop, and read in do-files of the other layout session route transcripts to keep the one central database as current as possible. Before reading in the do-files the main design container needs to return to the default settings that all the other layout people initiated their routes from. After all do-files are read in, new copies are created and routing continues.

This is it in a nut shell. Our presentation "Concurrent Board Layout Design" will be broken down into smaller details, it will entail a checklist and flowchart documenting all the steps required, and highlight ing the pitfalls to be weary of.

Bio:
Raisa Wesenberg is the Manager of the PCBA Design Group of Seagate Technology in Moorpark, Ca.

Janice Newhart is a Senior Advisory Development Engineer in the PCBA Design Group of Seagate Technology in Moorpark, Ca. She has been involved in various PCB CAD Systems since 1980. Since joining Seagate, Janice has been responsible for the deployment of the Mentor Graphics Board Station tool Suite & it's customization as well as designing boards.