This paper describes a methodology and a VHDL netlist program to generate or add VHDL models to Mentor Design Architect (DA) libraries using only VHDL constructs. The netlist program generates a VHDL netlist from a DA schematic that can be simulated with QuickHDL or another IEEE 1076 compliant simulator. The methodology and netlist program eliminates:

• The need to modify existing symbols
• Adding additional properties to symbols or LMS catalog files
• Use of viewpoints
• Use of Location Maps and hard coded paths
• Need to generate sheet based models

The methodology and netlist program includes the following features:

• Allows managing of an ASCII VHDL library
• Uses a search path for locating models based on component and symbol names
• No need to enter DA to change a simulation model
• Easier to create, maintain and modify VHDL libraries verses sheet based models
• Uses VHDL configurations to encapsulate "off-the-shelf" models
• Allows multiple modeling techniques such as VHDL behavioral, Synopsys LMG C, VHDL and Hardware models
• Modifies illegal VHDL pin names in VHDL netlist
• Allows the passing user added properties to DA symbols as VHDL generics.
• Run from UNIX shell

The netlist program called "abvhdlnet" was written using Connectivity Data Port (CDP). CDP implements the CAD Framework Initiative Design Representation (CFI-DR) procedural interface for Mentor EDDM based designs. In basic terms, the paper describes the algorithms and usage of the program and CDP functions.

Knowledge of VHDL, C programming language and UNIX Bourne shell are assumed. Users not proficient with these programs will benefit from the methodology and functionality of the netlist program.

Bio:
Inna Lyusternik is pursuing her BS in Electrical Engineering at Case Western Reserve University. She will graduate in the Fall 1997 semester. Inna has been a co-op and has served as an intern at Allen-Bradley from 1996 to 1997 working on Allen-Bradley's LMS Library and adding VHDL models to the library. Inna previously worked in the Electronic Design Center at Case Western University.

Dan Weyer received his BS from Cleveland State University in 1981 and is currently pursuing MS in Computer Engineering at Case Western University (hopefully December 97). Dan is a CAE Project Engineer at Allen-Bradley in Mayfield Heights Ohio. He has been working in EDA field for the past 10 years at Allen-Bradley and with Mentor tools since 1991. Dan previously worked as a Design Engineer with Picker International in the CT and MRI Division.