This paper describes the challenges and successes encountered in the process of transitioning from Dracula to ICverify to Calibre for verifying large mixed-signal designs. The author's group was able to convert rapidly to ICverify (SVRF format) from an existing Dracula deck and to reuse this rules file in establishing rules files for two additional wafer fab processes. The transition from ICverify to Calibre required no additional rules deck development and added much needed functionality and capacity.

The flexibility of the device recognition language allowed recognition of a diverse mixture of analog and digital devices required in our mixed-signal designs. Calibre's extensive filtering options allowed us to verify design blocks with a large number of unused or extra devices, defined in either layout or schematic, which were implemented to allow for easy adaption to variations in developing processes.

The hierarchical LVS capabilities provided the capacity to verify a 5.1 million transistor mixed-signal design in four hours. Other verification tools available to our group have not even been able to complete a run on this design.

We were also able to dramatically improve the accuracy of our parasitics modeling. Using the feature set of ICextract and xCalibre, we have been able to directly implement the same parasitics modeling equations used in our simulations and to apply these, without approximation, to the real layout. Accuracy in modeling these parasitics has become a critical point in achieving first silicon functionality.

Bio:
Pat LaCour is a Senior Staff Scientist for Motorola, Inc. in Austin, TX. He has been with Motorola since 1988. His current responsibilties include layout verification and parasitics modeling support for the Communications Transmission and Access Division, Semiconductor Sector. He holds a BS in Physics from Texas A&M University and a MSEE from the University of Texas at Austin.