Over the past few years, signal integrity issues are being brought to the forefront of PCB design. Many EDA vendors have released signal integrity analysis and floorplanner tools over the past few years. However, the problem persists... How do users implement these new technologies into an already complex PCB design flow.

Signal integrity simulation is a lot more imvolved than merely buying a tool from an EDA vender. These tools are not your proverbial plug-and-play variety software. They are very dependent on the user's knowledge of the circuit and software, as well as the accuracy of the models being used.

This paper will teach PCB designers about signal integrity and explain all the "black magic" engineers are throwing at them. The intent of this paper is to help PCB designers understand why signal integrity is rearing its head more and more, and what all these constraints mean to the performance of the circuit. Finally, this paper will help PCB designers understand that they are not there just to tie the hands of the designer. The premis is that designers will do a better job if they understand where all this is coming from (rather than seeing it as a list of "Do this . . .")

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